qemu/target/i386/tcg
Paolo Bonzini c46f68bd7d target/i386: pcrel: store low bits of physical address in data[0]
For PC-relative translation blocks, env->eip changes during the
execution of a translation block, Therefore, QEMU must be able to
recover an instruction's PC just from the TranslationBlock struct and
the instruction data with.  Because a TB will not span two pages, QEMU
stores all the low bits of EIP in the instruction data and replaces them
in x86_restore_state_to_opc.  Bits 12 and higher (which may vary between
executions of a PCREL TB, since these only use the physical address in
the hash key) are kept unmodified from env->eip.  The assumption is that
these bits of EIP, unlike bits 0-11, will not change as the translation
block executes.

Unfortunately, this is incorrect when the CS base is not aligned to a page.
Then the linear address of the instructions (i.e. the one with the
CS base addred) indeed will never span two pages, but bits 12+ of EIP
can actually change.  For example, if CS base is 0x80262200 and EIP =
0x6FF4, the first instruction in the translation block will be at linear
address 0x802691F4.  Even a very small TB will cross to EIP = 0x7xxx,
while the linear addresses will remain comfortably within a single page.

The fix is simply to use the low bits of the linear address for data[0],
since those don't change.  Then x86_restore_state_to_opc uses tb->cs_base
to compute a temporary linear address (referring to some unknown
instruction in the TB, but with the correct values of bits 12 and higher);
the low bits are replaced with data[0], and EIP is obtained by subtracting
again the CS base.

Huge thanks to Mark Cave-Ayland for the image and initial debugging,
and to Gitlab user @kjliew for help with bisecting another occurrence
of (hopefully!) the same bug.

It should be relatively easy to write a testcase that performs MMIO on
an EIP with different bits 12+ than the first instruction of the translation
block; any help is welcome.

Fixes: e3a79e0e87 ("target/i386: Enable TARGET_TB_PCREL", 2022-10-11)
Cc: qemu-stable@nongnu.org
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Cc: Richard Henderson <richard.henderson@linaro.org>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1759
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1964
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2012
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
(cherry picked from commit 729ba8e933)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-01-20 12:24:50 +03:00
..
sysemu accel/tcg: Replace CPUState.env_ptr with cpu_env() 2023-10-04 11:03:54 -07:00
user target/i386: implement SYSCALL/SYSRET in 32-bit emulators 2023-06-26 10:23:56 +02:00
bpt_helper.c compiler.h: replace QEMU_NORETURN with G_NORETURN 2022-04-21 17:03:51 +04:00
cc_helper_template.h.inc target/i386: Rename helper template headers as '.h.inc' 2023-06-13 11:28:58 +02:00
cc_helper.c target/i386: Rename helper template headers as '.h.inc' 2023-06-13 11:28:58 +02:00
decode-new.c.inc target/i386: validate VEX.W for AVX instructions 2023-10-25 17:35:07 +02:00
decode-new.h target/i386: validate VEX.W for AVX instructions 2023-10-25 17:35:07 +02:00
emit.c.inc target/i386: group common checks in the decoding phase 2023-10-25 17:35:07 +02:00
excp_helper.c target/i386: Raise #GP on unaligned m128 accesses when required. 2022-09-18 09:17:40 +02:00
fpu_helper.c target/translate: Include missing 'exec/cpu_ldst.h' header 2023-08-31 19:47:43 +02:00
helper-tcg.h target/i386: Raise #GP on unaligned m128 accesses when required. 2022-09-18 09:17:40 +02:00
int_helper.c target/i386: Rename helper template headers as '.h.inc' 2023-06-13 11:28:58 +02:00
mem_helper.c target/i386: Inline cmpxchg16b 2023-02-04 06:19:43 -10:00
meson.build i386: split svm_helper into sysemu and stub-only user 2021-05-10 15:41:51 -04:00
misc_helper.c target/i386: Check for USER_ONLY definition instead of SOFTMMU one 2023-10-07 19:02:33 +02:00
mpx_helper.c i386: move TCG cpu class initialization to tcg/ 2020-12-16 15:50:33 -05:00
ops_sse_header.h.inc target/i386: implement SHA instructions 2023-10-25 17:35:07 +02:00
seg_helper.c target/i386: fix shadowed variable pasto 2023-10-12 16:37:31 +02:00
seg_helper.h i386: split seg_helper into user-only and sysemu parts 2021-05-10 15:41:52 -04:00
shift_helper_template.h.inc target/i386: Rename helper template headers as '.h.inc' 2023-06-13 11:28:58 +02:00
tcg-cpu.c target/i386: pcrel: store low bits of physical address in data[0] 2024-01-20 12:24:50 +03:00
tcg-cpu.h target/i386: Move X86XSaveArea into TCG 2021-07-06 08:33:51 +02:00
tcg-stub.c
translate.c target/i386: pcrel: store low bits of physical address in data[0] 2024-01-20 12:24:50 +03:00