673b2d42a8
The nRF51 is a Cortex-M0 microcontroller with an on-board radio module, plus other common ARM SoC peripherals. http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf This defines a basic model of the CPU and memory, with no peripherals implemented at this stage. Signed-off-by: Joel Stanley <joel@jms.id.au> Message-id: 20180831220920.27113-3-joel@jms.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: wrapped a few long lines] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
134 lines
3.8 KiB
C
134 lines
3.8 KiB
C
/*
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* Nordic Semiconductor nRF51 SoC
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* http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf
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*
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* Copyright 2018 Joel Stanley <joel@jms.id.au>
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu-common.h"
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#include "hw/arm/arm.h"
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#include "hw/sysbus.h"
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#include "hw/boards.h"
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#include "hw/devices.h"
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#include "hw/misc/unimp.h"
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#include "exec/address-spaces.h"
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#include "sysemu/sysemu.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "hw/arm/nrf51_soc.h"
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#define IOMEM_BASE 0x40000000
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#define IOMEM_SIZE 0x20000000
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#define FICR_BASE 0x10000000
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#define FICR_SIZE 0x000000fc
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#define FLASH_BASE 0x00000000
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#define SRAM_BASE 0x20000000
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#define PRIVATE_BASE 0xF0000000
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#define PRIVATE_SIZE 0x10000000
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/*
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* The size and base is for the NRF51822 part. If other parts
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* are supported in the future, add a sub-class of NRF51SoC for
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* the specific variants
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*/
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#define NRF51822_FLASH_SIZE (256 * 1024)
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#define NRF51822_SRAM_SIZE (16 * 1024)
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static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
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{
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NRF51State *s = NRF51_SOC(dev_soc);
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Error *err = NULL;
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if (!s->board_memory) {
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error_setg(errp, "memory property was not set");
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return;
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}
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object_property_set_link(OBJECT(&s->cpu), OBJECT(&s->container), "memory",
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&err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
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memory_region_init_rom(&s->flash, OBJECT(s), "nrf51.flash", s->flash_size,
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&err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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memory_region_add_subregion(&s->container, FLASH_BASE, &s->flash);
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memory_region_init_ram(&s->sram, NULL, "nrf51.sram", s->sram_size, &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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memory_region_add_subregion(&s->container, SRAM_BASE, &s->sram);
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create_unimplemented_device("nrf51_soc.io", IOMEM_BASE, IOMEM_SIZE);
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create_unimplemented_device("nrf51_soc.ficr", FICR_BASE, FICR_SIZE);
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create_unimplemented_device("nrf51_soc.private",
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PRIVATE_BASE, PRIVATE_SIZE);
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}
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static void nrf51_soc_init(Object *obj)
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{
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NRF51State *s = NRF51_SOC(obj);
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memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX);
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sysbus_init_child_obj(OBJECT(s), "armv6m", OBJECT(&s->cpu), sizeof(s->cpu),
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TYPE_ARMV7M);
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qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",
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ARM_CPU_TYPE_NAME("cortex-m0"));
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qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);
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}
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static Property nrf51_soc_properties[] = {
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DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION,
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MemoryRegion *),
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DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE),
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DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size,
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NRF51822_FLASH_SIZE),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void nrf51_soc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = nrf51_soc_realize;
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dc->props = nrf51_soc_properties;
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}
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static const TypeInfo nrf51_soc_info = {
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.name = TYPE_NRF51_SOC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(NRF51State),
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.instance_init = nrf51_soc_init,
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.class_init = nrf51_soc_class_init,
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};
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static void nrf51_soc_types(void)
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{
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type_register_static(&nrf51_soc_info);
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}
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type_init(nrf51_soc_types)
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