27ea1bc077
LL/SC opcodes have been removed from the Release 6. Add a single decodetree entry for the opcodes, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() calls. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-14-f4bug@amsat.org>
37 lines
1.4 KiB
Plaintext
37 lines
1.4 KiB
Plaintext
# MIPS32 Release 6 instruction set
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#
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# Copyright (C) 2020 Philippe Mathieu-Daudé
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#
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# SPDX-License-Identifier: LGPL-2.1-or-later
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#
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# Reference:
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# MIPS Architecture for Programmers Volume II-A
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# The MIPS32 Instruction Set Reference Manual, Revision 6.06
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# (Document Number: MD00086-2B-MIPS32BIS-AFP-06.06)
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#
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&rtype rs rt rd sa
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@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype
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LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
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REMOVED 010011 ----- ----- ----- ----- ------ # COP1X (COP3)
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REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2
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REMOVED 011111 ----- ----- ---------- 011001 # LWLE
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REMOVED 011111 ----- ----- ---------- 011010 # LWRE
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REMOVED 011111 ----- ----- ---------- 100001 # SWLE
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REMOVED 011111 ----- ----- ---------- 100010 # SWRE
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REMOVED 100010 ----- ----- ---------------- # LWL
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REMOVED 100110 ----- ----- ---------------- # LWR
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REMOVED 101010 ----- ----- ---------------- # SWL
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REMOVED 101110 ----- ----- ---------------- # SWR
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REMOVED 101111 ----- ----- ---------------- # CACHE
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REMOVED 110000 ----- ----- ---------------- # LL
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REMOVED 110011 ----- ----- ---------------- # PREF
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REMOVED 111000 ----- ----- ---------------- # SC
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