0573fbfc3f
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3210 c046a42c-6fe2-441c-8c8c-71466251a162
1048 lines
33 KiB
C
1048 lines
33 KiB
C
/*
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* i386 helpers (without register variable usage)
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdarg.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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#include <signal.h>
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#include <assert.h>
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#include "cpu.h"
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#include "exec-all.h"
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#include "svm.h"
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//#define DEBUG_MMU
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#ifdef USE_CODE_COPY
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#include <asm/ldt.h>
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#include <linux/unistd.h>
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#include <linux/version.h>
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int modify_ldt(int func, void *ptr, unsigned long bytecount)
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{
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return syscall(__NR_modify_ldt, func, ptr, bytecount);
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}
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#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 5, 66)
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#define modify_ldt_ldt_s user_desc
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#endif
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#endif /* USE_CODE_COPY */
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CPUX86State *cpu_x86_init(void)
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{
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CPUX86State *env;
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static int inited;
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env = qemu_mallocz(sizeof(CPUX86State));
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if (!env)
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return NULL;
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cpu_exec_init(env);
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/* init various static tables */
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if (!inited) {
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inited = 1;
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optimize_flags_init();
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}
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#ifdef USE_CODE_COPY
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/* testing code for code copy case */
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{
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struct modify_ldt_ldt_s ldt;
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ldt.entry_number = 1;
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ldt.base_addr = (unsigned long)env;
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ldt.limit = (sizeof(CPUState) + 0xfff) >> 12;
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ldt.seg_32bit = 1;
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ldt.contents = MODIFY_LDT_CONTENTS_DATA;
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ldt.read_exec_only = 0;
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ldt.limit_in_pages = 1;
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ldt.seg_not_present = 0;
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ldt.useable = 1;
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modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
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asm volatile ("movl %0, %%fs" : : "r" ((1 << 3) | 7));
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}
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#endif
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{
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int family, model, stepping;
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#ifdef TARGET_X86_64
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env->cpuid_vendor1 = 0x68747541; /* "Auth" */
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env->cpuid_vendor2 = 0x69746e65; /* "enti" */
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env->cpuid_vendor3 = 0x444d4163; /* "cAMD" */
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family = 6;
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model = 2;
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stepping = 3;
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#else
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env->cpuid_vendor1 = 0x756e6547; /* "Genu" */
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env->cpuid_vendor2 = 0x49656e69; /* "ineI" */
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env->cpuid_vendor3 = 0x6c65746e; /* "ntel" */
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#if 0
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/* pentium 75-200 */
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family = 5;
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model = 2;
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stepping = 11;
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#else
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/* pentium pro */
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family = 6;
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model = 3;
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stepping = 3;
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#endif
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#endif
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env->cpuid_level = 2;
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env->cpuid_version = (family << 8) | (model << 4) | stepping;
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env->cpuid_features = (CPUID_FP87 | CPUID_DE | CPUID_PSE |
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CPUID_TSC | CPUID_MSR | CPUID_MCE |
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CPUID_CX8 | CPUID_PGE | CPUID_CMOV |
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CPUID_PAT);
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env->pat = 0x0007040600070406ULL;
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env->cpuid_ext3_features = CPUID_EXT3_SVM;
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env->cpuid_ext_features = CPUID_EXT_SSE3;
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env->cpuid_features |= CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | CPUID_PAE | CPUID_SEP;
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env->cpuid_features |= CPUID_APIC;
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env->cpuid_xlevel = 0x8000000e;
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{
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const char *model_id = "QEMU Virtual CPU version " QEMU_VERSION;
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int c, len, i;
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len = strlen(model_id);
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for(i = 0; i < 48; i++) {
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if (i >= len)
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c = '\0';
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else
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c = model_id[i];
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env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
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}
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}
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#ifdef TARGET_X86_64
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/* currently not enabled for std i386 because not fully tested */
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env->cpuid_ext2_features = (env->cpuid_features & 0x0183F3FF);
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env->cpuid_ext2_features |= CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX;
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/* these features are needed for Win64 and aren't fully implemented */
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env->cpuid_features |= CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA;
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/* this feature is needed for Solaris and isn't fully implemented */
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env->cpuid_features |= CPUID_PSE36;
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#endif
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}
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cpu_reset(env);
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#ifdef USE_KQEMU
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kqemu_init(env);
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#endif
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return env;
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}
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/* NOTE: must be called outside the CPU execute loop */
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void cpu_reset(CPUX86State *env)
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{
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int i;
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memset(env, 0, offsetof(CPUX86State, breakpoints));
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tlb_flush(env, 1);
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env->old_exception = -1;
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/* init to reset state */
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#ifdef CONFIG_SOFTMMU
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env->hflags |= HF_SOFTMMU_MASK;
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#endif
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env->hflags |= HF_GIF_MASK;
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cpu_x86_update_cr0(env, 0x60000010);
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env->a20_mask = 0xffffffff;
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env->smbase = 0x30000;
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env->idt.limit = 0xffff;
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env->gdt.limit = 0xffff;
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env->ldt.limit = 0xffff;
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env->ldt.flags = DESC_P_MASK;
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env->tr.limit = 0xffff;
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env->tr.flags = DESC_P_MASK;
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cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 0);
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cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 0);
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cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 0);
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cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 0);
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cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 0);
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cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 0);
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env->eip = 0xfff0;
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env->regs[R_EDX] = 0x600; /* indicate P6 processor */
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env->eflags = 0x2;
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/* FPU init */
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for(i = 0;i < 8; i++)
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env->fptags[i] = 1;
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env->fpuc = 0x37f;
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env->mxcsr = 0x1f80;
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}
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void cpu_x86_close(CPUX86State *env)
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{
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free(env);
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}
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/***********************************************************/
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/* x86 debug */
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static const char *cc_op_str[] = {
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"DYNAMIC",
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"EFLAGS",
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"MULB",
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"MULW",
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"MULL",
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"MULQ",
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"ADDB",
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"ADDW",
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"ADDL",
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"ADDQ",
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"ADCB",
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"ADCW",
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"ADCL",
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"ADCQ",
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"SUBB",
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"SUBW",
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"SUBL",
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"SUBQ",
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"SBBB",
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"SBBW",
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"SBBL",
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"SBBQ",
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"LOGICB",
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"LOGICW",
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"LOGICL",
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"LOGICQ",
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"INCB",
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"INCW",
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"INCL",
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"INCQ",
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"DECB",
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"DECW",
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"DECL",
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"DECQ",
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"SHLB",
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"SHLW",
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"SHLL",
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"SHLQ",
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"SARB",
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"SARW",
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"SARL",
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"SARQ",
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};
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void cpu_dump_state(CPUState *env, FILE *f,
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int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
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int flags)
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{
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int eflags, i, nb;
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char cc_op_name[32];
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static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };
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eflags = env->eflags;
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#ifdef TARGET_X86_64
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if (env->hflags & HF_CS64_MASK) {
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cpu_fprintf(f,
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"RAX=%016" PRIx64 " RBX=%016" PRIx64 " RCX=%016" PRIx64 " RDX=%016" PRIx64 "\n"
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"RSI=%016" PRIx64 " RDI=%016" PRIx64 " RBP=%016" PRIx64 " RSP=%016" PRIx64 "\n"
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"R8 =%016" PRIx64 " R9 =%016" PRIx64 " R10=%016" PRIx64 " R11=%016" PRIx64 "\n"
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"R12=%016" PRIx64 " R13=%016" PRIx64 " R14=%016" PRIx64 " R15=%016" PRIx64 "\n"
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"RIP=%016" PRIx64 " RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
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env->regs[R_EAX],
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env->regs[R_EBX],
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env->regs[R_ECX],
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env->regs[R_EDX],
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env->regs[R_ESI],
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env->regs[R_EDI],
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env->regs[R_EBP],
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env->regs[R_ESP],
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env->regs[8],
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env->regs[9],
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env->regs[10],
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env->regs[11],
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env->regs[12],
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env->regs[13],
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env->regs[14],
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env->regs[15],
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env->eip, eflags,
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eflags & DF_MASK ? 'D' : '-',
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eflags & CC_O ? 'O' : '-',
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eflags & CC_S ? 'S' : '-',
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eflags & CC_Z ? 'Z' : '-',
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eflags & CC_A ? 'A' : '-',
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eflags & CC_P ? 'P' : '-',
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eflags & CC_C ? 'C' : '-',
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env->hflags & HF_CPL_MASK,
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(env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
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(env->a20_mask >> 20) & 1,
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(env->hflags >> HF_SMM_SHIFT) & 1,
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(env->hflags >> HF_HALTED_SHIFT) & 1);
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} else
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#endif
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{
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cpu_fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
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"ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
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"EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
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(uint32_t)env->regs[R_EAX],
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(uint32_t)env->regs[R_EBX],
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(uint32_t)env->regs[R_ECX],
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(uint32_t)env->regs[R_EDX],
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(uint32_t)env->regs[R_ESI],
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(uint32_t)env->regs[R_EDI],
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(uint32_t)env->regs[R_EBP],
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(uint32_t)env->regs[R_ESP],
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(uint32_t)env->eip, eflags,
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eflags & DF_MASK ? 'D' : '-',
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eflags & CC_O ? 'O' : '-',
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eflags & CC_S ? 'S' : '-',
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eflags & CC_Z ? 'Z' : '-',
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eflags & CC_A ? 'A' : '-',
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eflags & CC_P ? 'P' : '-',
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eflags & CC_C ? 'C' : '-',
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env->hflags & HF_CPL_MASK,
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(env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
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(env->a20_mask >> 20) & 1,
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(env->hflags >> HF_SMM_SHIFT) & 1,
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(env->hflags >> HF_HALTED_SHIFT) & 1);
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}
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#ifdef TARGET_X86_64
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if (env->hflags & HF_LMA_MASK) {
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for(i = 0; i < 6; i++) {
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SegmentCache *sc = &env->segs[i];
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cpu_fprintf(f, "%s =%04x %016" PRIx64 " %08x %08x\n",
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seg_name[i],
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sc->selector,
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sc->base,
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sc->limit,
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sc->flags);
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}
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cpu_fprintf(f, "LDT=%04x %016" PRIx64 " %08x %08x\n",
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env->ldt.selector,
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env->ldt.base,
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env->ldt.limit,
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env->ldt.flags);
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cpu_fprintf(f, "TR =%04x %016" PRIx64 " %08x %08x\n",
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env->tr.selector,
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env->tr.base,
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env->tr.limit,
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env->tr.flags);
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cpu_fprintf(f, "GDT= %016" PRIx64 " %08x\n",
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env->gdt.base, env->gdt.limit);
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cpu_fprintf(f, "IDT= %016" PRIx64 " %08x\n",
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env->idt.base, env->idt.limit);
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cpu_fprintf(f, "CR0=%08x CR2=%016" PRIx64 " CR3=%016" PRIx64 " CR4=%08x\n",
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(uint32_t)env->cr[0],
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env->cr[2],
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env->cr[3],
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(uint32_t)env->cr[4]);
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} else
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#endif
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{
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for(i = 0; i < 6; i++) {
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SegmentCache *sc = &env->segs[i];
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cpu_fprintf(f, "%s =%04x %08x %08x %08x\n",
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seg_name[i],
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sc->selector,
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(uint32_t)sc->base,
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sc->limit,
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sc->flags);
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}
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cpu_fprintf(f, "LDT=%04x %08x %08x %08x\n",
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env->ldt.selector,
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(uint32_t)env->ldt.base,
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env->ldt.limit,
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env->ldt.flags);
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cpu_fprintf(f, "TR =%04x %08x %08x %08x\n",
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env->tr.selector,
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(uint32_t)env->tr.base,
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env->tr.limit,
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env->tr.flags);
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cpu_fprintf(f, "GDT= %08x %08x\n",
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(uint32_t)env->gdt.base, env->gdt.limit);
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cpu_fprintf(f, "IDT= %08x %08x\n",
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(uint32_t)env->idt.base, env->idt.limit);
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cpu_fprintf(f, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
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(uint32_t)env->cr[0],
|
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(uint32_t)env->cr[2],
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(uint32_t)env->cr[3],
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(uint32_t)env->cr[4]);
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}
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if (flags & X86_DUMP_CCOP) {
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if ((unsigned)env->cc_op < CC_OP_NB)
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snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->cc_op]);
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else
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snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op);
|
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#ifdef TARGET_X86_64
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if (env->hflags & HF_CS64_MASK) {
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cpu_fprintf(f, "CCS=%016" PRIx64 " CCD=%016" PRIx64 " CCO=%-8s\n",
|
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env->cc_src, env->cc_dst,
|
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cc_op_name);
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} else
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#endif
|
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{
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cpu_fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n",
|
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(uint32_t)env->cc_src, (uint32_t)env->cc_dst,
|
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cc_op_name);
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}
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|
}
|
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if (flags & X86_DUMP_FPU) {
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int fptag;
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fptag = 0;
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for(i = 0; i < 8; i++) {
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fptag |= ((!env->fptags[i]) << i);
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}
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cpu_fprintf(f, "FCW=%04x FSW=%04x [ST=%d] FTW=%02x MXCSR=%08x\n",
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env->fpuc,
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(env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11,
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env->fpstt,
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fptag,
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env->mxcsr);
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for(i=0;i<8;i++) {
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|
#if defined(USE_X86LDOUBLE)
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union {
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long double d;
|
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struct {
|
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uint64_t lower;
|
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uint16_t upper;
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} l;
|
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} tmp;
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tmp.d = env->fpregs[i].d;
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cpu_fprintf(f, "FPR%d=%016" PRIx64 " %04x",
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i, tmp.l.lower, tmp.l.upper);
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#else
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cpu_fprintf(f, "FPR%d=%016" PRIx64,
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i, env->fpregs[i].mmx.q);
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#endif
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if ((i & 1) == 1)
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cpu_fprintf(f, "\n");
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else
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cpu_fprintf(f, " ");
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}
|
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if (env->hflags & HF_CS64_MASK)
|
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nb = 16;
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else
|
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nb = 8;
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for(i=0;i<nb;i++) {
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cpu_fprintf(f, "XMM%02d=%08x%08x%08x%08x",
|
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i,
|
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env->xmm_regs[i].XMM_L(3),
|
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env->xmm_regs[i].XMM_L(2),
|
|
env->xmm_regs[i].XMM_L(1),
|
|
env->xmm_regs[i].XMM_L(0));
|
|
if ((i & 1) == 1)
|
|
cpu_fprintf(f, "\n");
|
|
else
|
|
cpu_fprintf(f, " ");
|
|
}
|
|
}
|
|
}
|
|
|
|
/***********************************************************/
|
|
/* x86 mmu */
|
|
/* XXX: add PGE support */
|
|
|
|
void cpu_x86_set_a20(CPUX86State *env, int a20_state)
|
|
{
|
|
a20_state = (a20_state != 0);
|
|
if (a20_state != ((env->a20_mask >> 20) & 1)) {
|
|
#if defined(DEBUG_MMU)
|
|
printf("A20 update: a20=%d\n", a20_state);
|
|
#endif
|
|
/* if the cpu is currently executing code, we must unlink it and
|
|
all the potentially executing TB */
|
|
cpu_interrupt(env, CPU_INTERRUPT_EXITTB);
|
|
|
|
/* when a20 is changed, all the MMU mappings are invalid, so
|
|
we must flush everything */
|
|
tlb_flush(env, 1);
|
|
env->a20_mask = 0xffefffff | (a20_state << 20);
|
|
}
|
|
}
|
|
|
|
void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
|
|
{
|
|
int pe_state;
|
|
|
|
#if defined(DEBUG_MMU)
|
|
printf("CR0 update: CR0=0x%08x\n", new_cr0);
|
|
#endif
|
|
if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) !=
|
|
(env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) {
|
|
tlb_flush(env, 1);
|
|
}
|
|
|
|
#ifdef TARGET_X86_64
|
|
if (!(env->cr[0] & CR0_PG_MASK) && (new_cr0 & CR0_PG_MASK) &&
|
|
(env->efer & MSR_EFER_LME)) {
|
|
/* enter in long mode */
|
|
/* XXX: generate an exception */
|
|
if (!(env->cr[4] & CR4_PAE_MASK))
|
|
return;
|
|
env->efer |= MSR_EFER_LMA;
|
|
env->hflags |= HF_LMA_MASK;
|
|
} else if ((env->cr[0] & CR0_PG_MASK) && !(new_cr0 & CR0_PG_MASK) &&
|
|
(env->efer & MSR_EFER_LMA)) {
|
|
/* exit long mode */
|
|
env->efer &= ~MSR_EFER_LMA;
|
|
env->hflags &= ~(HF_LMA_MASK | HF_CS64_MASK);
|
|
env->eip &= 0xffffffff;
|
|
}
|
|
#endif
|
|
env->cr[0] = new_cr0 | CR0_ET_MASK;
|
|
|
|
/* update PE flag in hidden flags */
|
|
pe_state = (env->cr[0] & CR0_PE_MASK);
|
|
env->hflags = (env->hflags & ~HF_PE_MASK) | (pe_state << HF_PE_SHIFT);
|
|
/* ensure that ADDSEG is always set in real mode */
|
|
env->hflags |= ((pe_state ^ 1) << HF_ADDSEG_SHIFT);
|
|
/* update FPU flags */
|
|
env->hflags = (env->hflags & ~(HF_MP_MASK | HF_EM_MASK | HF_TS_MASK)) |
|
|
((new_cr0 << (HF_MP_SHIFT - 1)) & (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK));
|
|
}
|
|
|
|
/* XXX: in legacy PAE mode, generate a GPF if reserved bits are set in
|
|
the PDPT */
|
|
void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3)
|
|
{
|
|
env->cr[3] = new_cr3;
|
|
if (env->cr[0] & CR0_PG_MASK) {
|
|
#if defined(DEBUG_MMU)
|
|
printf("CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3);
|
|
#endif
|
|
tlb_flush(env, 0);
|
|
}
|
|
}
|
|
|
|
void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
|
|
{
|
|
#if defined(DEBUG_MMU)
|
|
printf("CR4 update: CR4=%08x\n", (uint32_t)env->cr[4]);
|
|
#endif
|
|
if ((new_cr4 & (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK)) !=
|
|
(env->cr[4] & (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK))) {
|
|
tlb_flush(env, 1);
|
|
}
|
|
/* SSE handling */
|
|
if (!(env->cpuid_features & CPUID_SSE))
|
|
new_cr4 &= ~CR4_OSFXSR_MASK;
|
|
if (new_cr4 & CR4_OSFXSR_MASK)
|
|
env->hflags |= HF_OSFXSR_MASK;
|
|
else
|
|
env->hflags &= ~HF_OSFXSR_MASK;
|
|
|
|
env->cr[4] = new_cr4;
|
|
}
|
|
|
|
/* XXX: also flush 4MB pages */
|
|
void cpu_x86_flush_tlb(CPUX86State *env, target_ulong addr)
|
|
{
|
|
tlb_flush_page(env, addr);
|
|
}
|
|
|
|
#if defined(CONFIG_USER_ONLY)
|
|
|
|
int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
|
|
int is_write, int is_user, int is_softmmu)
|
|
{
|
|
/* user mode only emulation */
|
|
is_write &= 1;
|
|
env->cr[2] = addr;
|
|
env->error_code = (is_write << PG_ERROR_W_BIT);
|
|
env->error_code |= PG_ERROR_U_MASK;
|
|
env->exception_index = EXCP0E_PAGE;
|
|
return 1;
|
|
}
|
|
|
|
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
|
|
{
|
|
return addr;
|
|
}
|
|
|
|
#else
|
|
|
|
#define PHYS_ADDR_MASK 0xfffff000
|
|
|
|
/* return value:
|
|
-1 = cannot handle fault
|
|
0 = nothing more to do
|
|
1 = generate PF fault
|
|
2 = soft MMU activation required for this block
|
|
*/
|
|
int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
|
|
int is_write1, int is_user, int is_softmmu)
|
|
{
|
|
uint64_t ptep, pte;
|
|
uint32_t pdpe_addr, pde_addr, pte_addr;
|
|
int error_code, is_dirty, prot, page_size, ret, is_write;
|
|
unsigned long paddr, page_offset;
|
|
target_ulong vaddr, virt_addr;
|
|
|
|
#if defined(DEBUG_MMU)
|
|
printf("MMU fault: addr=" TARGET_FMT_lx " w=%d u=%d eip=" TARGET_FMT_lx "\n",
|
|
addr, is_write1, is_user, env->eip);
|
|
#endif
|
|
is_write = is_write1 & 1;
|
|
|
|
if (!(env->cr[0] & CR0_PG_MASK)) {
|
|
pte = addr;
|
|
virt_addr = addr & TARGET_PAGE_MASK;
|
|
prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
|
|
page_size = 4096;
|
|
goto do_mapping;
|
|
}
|
|
|
|
if (env->cr[4] & CR4_PAE_MASK) {
|
|
uint64_t pde, pdpe;
|
|
|
|
/* XXX: we only use 32 bit physical addresses */
|
|
#ifdef TARGET_X86_64
|
|
if (env->hflags & HF_LMA_MASK) {
|
|
uint32_t pml4e_addr;
|
|
uint64_t pml4e;
|
|
int32_t sext;
|
|
|
|
/* test virtual address sign extension */
|
|
sext = (int64_t)addr >> 47;
|
|
if (sext != 0 && sext != -1) {
|
|
env->error_code = 0;
|
|
env->exception_index = EXCP0D_GPF;
|
|
return 1;
|
|
}
|
|
|
|
pml4e_addr = ((env->cr[3] & ~0xfff) + (((addr >> 39) & 0x1ff) << 3)) &
|
|
env->a20_mask;
|
|
pml4e = ldq_phys(pml4e_addr);
|
|
if (!(pml4e & PG_PRESENT_MASK)) {
|
|
error_code = 0;
|
|
goto do_fault;
|
|
}
|
|
if (!(env->efer & MSR_EFER_NXE) && (pml4e & PG_NX_MASK)) {
|
|
error_code = PG_ERROR_RSVD_MASK;
|
|
goto do_fault;
|
|
}
|
|
if (!(pml4e & PG_ACCESSED_MASK)) {
|
|
pml4e |= PG_ACCESSED_MASK;
|
|
stl_phys_notdirty(pml4e_addr, pml4e);
|
|
}
|
|
ptep = pml4e ^ PG_NX_MASK;
|
|
pdpe_addr = ((pml4e & PHYS_ADDR_MASK) + (((addr >> 30) & 0x1ff) << 3)) &
|
|
env->a20_mask;
|
|
pdpe = ldq_phys(pdpe_addr);
|
|
if (!(pdpe & PG_PRESENT_MASK)) {
|
|
error_code = 0;
|
|
goto do_fault;
|
|
}
|
|
if (!(env->efer & MSR_EFER_NXE) && (pdpe & PG_NX_MASK)) {
|
|
error_code = PG_ERROR_RSVD_MASK;
|
|
goto do_fault;
|
|
}
|
|
ptep &= pdpe ^ PG_NX_MASK;
|
|
if (!(pdpe & PG_ACCESSED_MASK)) {
|
|
pdpe |= PG_ACCESSED_MASK;
|
|
stl_phys_notdirty(pdpe_addr, pdpe);
|
|
}
|
|
} else
|
|
#endif
|
|
{
|
|
/* XXX: load them when cr3 is loaded ? */
|
|
pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) &
|
|
env->a20_mask;
|
|
pdpe = ldq_phys(pdpe_addr);
|
|
if (!(pdpe & PG_PRESENT_MASK)) {
|
|
error_code = 0;
|
|
goto do_fault;
|
|
}
|
|
ptep = PG_NX_MASK | PG_USER_MASK | PG_RW_MASK;
|
|
}
|
|
|
|
pde_addr = ((pdpe & PHYS_ADDR_MASK) + (((addr >> 21) & 0x1ff) << 3)) &
|
|
env->a20_mask;
|
|
pde = ldq_phys(pde_addr);
|
|
if (!(pde & PG_PRESENT_MASK)) {
|
|
error_code = 0;
|
|
goto do_fault;
|
|
}
|
|
if (!(env->efer & MSR_EFER_NXE) && (pde & PG_NX_MASK)) {
|
|
error_code = PG_ERROR_RSVD_MASK;
|
|
goto do_fault;
|
|
}
|
|
ptep &= pde ^ PG_NX_MASK;
|
|
if (pde & PG_PSE_MASK) {
|
|
/* 2 MB page */
|
|
page_size = 2048 * 1024;
|
|
ptep ^= PG_NX_MASK;
|
|
if ((ptep & PG_NX_MASK) && is_write1 == 2)
|
|
goto do_fault_protect;
|
|
if (is_user) {
|
|
if (!(ptep & PG_USER_MASK))
|
|
goto do_fault_protect;
|
|
if (is_write && !(ptep & PG_RW_MASK))
|
|
goto do_fault_protect;
|
|
} else {
|
|
if ((env->cr[0] & CR0_WP_MASK) &&
|
|
is_write && !(ptep & PG_RW_MASK))
|
|
goto do_fault_protect;
|
|
}
|
|
is_dirty = is_write && !(pde & PG_DIRTY_MASK);
|
|
if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
|
|
pde |= PG_ACCESSED_MASK;
|
|
if (is_dirty)
|
|
pde |= PG_DIRTY_MASK;
|
|
stl_phys_notdirty(pde_addr, pde);
|
|
}
|
|
/* align to page_size */
|
|
pte = pde & ((PHYS_ADDR_MASK & ~(page_size - 1)) | 0xfff);
|
|
virt_addr = addr & ~(page_size - 1);
|
|
} else {
|
|
/* 4 KB page */
|
|
if (!(pde & PG_ACCESSED_MASK)) {
|
|
pde |= PG_ACCESSED_MASK;
|
|
stl_phys_notdirty(pde_addr, pde);
|
|
}
|
|
pte_addr = ((pde & PHYS_ADDR_MASK) + (((addr >> 12) & 0x1ff) << 3)) &
|
|
env->a20_mask;
|
|
pte = ldq_phys(pte_addr);
|
|
if (!(pte & PG_PRESENT_MASK)) {
|
|
error_code = 0;
|
|
goto do_fault;
|
|
}
|
|
if (!(env->efer & MSR_EFER_NXE) && (pte & PG_NX_MASK)) {
|
|
error_code = PG_ERROR_RSVD_MASK;
|
|
goto do_fault;
|
|
}
|
|
/* combine pde and pte nx, user and rw protections */
|
|
ptep &= pte ^ PG_NX_MASK;
|
|
ptep ^= PG_NX_MASK;
|
|
if ((ptep & PG_NX_MASK) && is_write1 == 2)
|
|
goto do_fault_protect;
|
|
if (is_user) {
|
|
if (!(ptep & PG_USER_MASK))
|
|
goto do_fault_protect;
|
|
if (is_write && !(ptep & PG_RW_MASK))
|
|
goto do_fault_protect;
|
|
} else {
|
|
if ((env->cr[0] & CR0_WP_MASK) &&
|
|
is_write && !(ptep & PG_RW_MASK))
|
|
goto do_fault_protect;
|
|
}
|
|
is_dirty = is_write && !(pte & PG_DIRTY_MASK);
|
|
if (!(pte & PG_ACCESSED_MASK) || is_dirty) {
|
|
pte |= PG_ACCESSED_MASK;
|
|
if (is_dirty)
|
|
pte |= PG_DIRTY_MASK;
|
|
stl_phys_notdirty(pte_addr, pte);
|
|
}
|
|
page_size = 4096;
|
|
virt_addr = addr & ~0xfff;
|
|
pte = pte & (PHYS_ADDR_MASK | 0xfff);
|
|
}
|
|
} else {
|
|
uint32_t pde;
|
|
|
|
/* page directory entry */
|
|
pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) &
|
|
env->a20_mask;
|
|
pde = ldl_phys(pde_addr);
|
|
if (!(pde & PG_PRESENT_MASK)) {
|
|
error_code = 0;
|
|
goto do_fault;
|
|
}
|
|
/* if PSE bit is set, then we use a 4MB page */
|
|
if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
|
|
page_size = 4096 * 1024;
|
|
if (is_user) {
|
|
if (!(pde & PG_USER_MASK))
|
|
goto do_fault_protect;
|
|
if (is_write && !(pde & PG_RW_MASK))
|
|
goto do_fault_protect;
|
|
} else {
|
|
if ((env->cr[0] & CR0_WP_MASK) &&
|
|
is_write && !(pde & PG_RW_MASK))
|
|
goto do_fault_protect;
|
|
}
|
|
is_dirty = is_write && !(pde & PG_DIRTY_MASK);
|
|
if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
|
|
pde |= PG_ACCESSED_MASK;
|
|
if (is_dirty)
|
|
pde |= PG_DIRTY_MASK;
|
|
stl_phys_notdirty(pde_addr, pde);
|
|
}
|
|
|
|
pte = pde & ~( (page_size - 1) & ~0xfff); /* align to page_size */
|
|
ptep = pte;
|
|
virt_addr = addr & ~(page_size - 1);
|
|
} else {
|
|
if (!(pde & PG_ACCESSED_MASK)) {
|
|
pde |= PG_ACCESSED_MASK;
|
|
stl_phys_notdirty(pde_addr, pde);
|
|
}
|
|
|
|
/* page directory entry */
|
|
pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) &
|
|
env->a20_mask;
|
|
pte = ldl_phys(pte_addr);
|
|
if (!(pte & PG_PRESENT_MASK)) {
|
|
error_code = 0;
|
|
goto do_fault;
|
|
}
|
|
/* combine pde and pte user and rw protections */
|
|
ptep = pte & pde;
|
|
if (is_user) {
|
|
if (!(ptep & PG_USER_MASK))
|
|
goto do_fault_protect;
|
|
if (is_write && !(ptep & PG_RW_MASK))
|
|
goto do_fault_protect;
|
|
} else {
|
|
if ((env->cr[0] & CR0_WP_MASK) &&
|
|
is_write && !(ptep & PG_RW_MASK))
|
|
goto do_fault_protect;
|
|
}
|
|
is_dirty = is_write && !(pte & PG_DIRTY_MASK);
|
|
if (!(pte & PG_ACCESSED_MASK) || is_dirty) {
|
|
pte |= PG_ACCESSED_MASK;
|
|
if (is_dirty)
|
|
pte |= PG_DIRTY_MASK;
|
|
stl_phys_notdirty(pte_addr, pte);
|
|
}
|
|
page_size = 4096;
|
|
virt_addr = addr & ~0xfff;
|
|
}
|
|
}
|
|
/* the page can be put in the TLB */
|
|
prot = PAGE_READ;
|
|
if (!(ptep & PG_NX_MASK))
|
|
prot |= PAGE_EXEC;
|
|
if (pte & PG_DIRTY_MASK) {
|
|
/* only set write access if already dirty... otherwise wait
|
|
for dirty access */
|
|
if (is_user) {
|
|
if (ptep & PG_RW_MASK)
|
|
prot |= PAGE_WRITE;
|
|
} else {
|
|
if (!(env->cr[0] & CR0_WP_MASK) ||
|
|
(ptep & PG_RW_MASK))
|
|
prot |= PAGE_WRITE;
|
|
}
|
|
}
|
|
do_mapping:
|
|
pte = pte & env->a20_mask;
|
|
|
|
/* Even if 4MB pages, we map only one 4KB page in the cache to
|
|
avoid filling it too fast */
|
|
page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
|
|
paddr = (pte & TARGET_PAGE_MASK) + page_offset;
|
|
vaddr = virt_addr + page_offset;
|
|
|
|
ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
|
|
return ret;
|
|
do_fault_protect:
|
|
error_code = PG_ERROR_P_MASK;
|
|
do_fault:
|
|
error_code |= (is_write << PG_ERROR_W_BIT);
|
|
if (is_user)
|
|
error_code |= PG_ERROR_U_MASK;
|
|
if (is_write1 == 2 &&
|
|
(env->efer & MSR_EFER_NXE) &&
|
|
(env->cr[4] & CR4_PAE_MASK))
|
|
error_code |= PG_ERROR_I_D_MASK;
|
|
if (INTERCEPTEDl(_exceptions, 1 << EXCP0E_PAGE)) {
|
|
stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2), addr);
|
|
} else {
|
|
env->cr[2] = addr;
|
|
}
|
|
env->error_code = error_code;
|
|
env->exception_index = EXCP0E_PAGE;
|
|
/* the VMM will handle this */
|
|
if (INTERCEPTEDl(_exceptions, 1 << EXCP0E_PAGE))
|
|
return 2;
|
|
return 1;
|
|
}
|
|
|
|
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
|
|
{
|
|
uint32_t pde_addr, pte_addr;
|
|
uint32_t pde, pte, paddr, page_offset, page_size;
|
|
|
|
if (env->cr[4] & CR4_PAE_MASK) {
|
|
uint32_t pdpe_addr, pde_addr, pte_addr;
|
|
uint32_t pdpe;
|
|
|
|
/* XXX: we only use 32 bit physical addresses */
|
|
#ifdef TARGET_X86_64
|
|
if (env->hflags & HF_LMA_MASK) {
|
|
uint32_t pml4e_addr, pml4e;
|
|
int32_t sext;
|
|
|
|
/* test virtual address sign extension */
|
|
sext = (int64_t)addr >> 47;
|
|
if (sext != 0 && sext != -1)
|
|
return -1;
|
|
|
|
pml4e_addr = ((env->cr[3] & ~0xfff) + (((addr >> 39) & 0x1ff) << 3)) &
|
|
env->a20_mask;
|
|
pml4e = ldl_phys(pml4e_addr);
|
|
if (!(pml4e & PG_PRESENT_MASK))
|
|
return -1;
|
|
|
|
pdpe_addr = ((pml4e & ~0xfff) + (((addr >> 30) & 0x1ff) << 3)) &
|
|
env->a20_mask;
|
|
pdpe = ldl_phys(pdpe_addr);
|
|
if (!(pdpe & PG_PRESENT_MASK))
|
|
return -1;
|
|
} else
|
|
#endif
|
|
{
|
|
pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) &
|
|
env->a20_mask;
|
|
pdpe = ldl_phys(pdpe_addr);
|
|
if (!(pdpe & PG_PRESENT_MASK))
|
|
return -1;
|
|
}
|
|
|
|
pde_addr = ((pdpe & ~0xfff) + (((addr >> 21) & 0x1ff) << 3)) &
|
|
env->a20_mask;
|
|
pde = ldl_phys(pde_addr);
|
|
if (!(pde & PG_PRESENT_MASK)) {
|
|
return -1;
|
|
}
|
|
if (pde & PG_PSE_MASK) {
|
|
/* 2 MB page */
|
|
page_size = 2048 * 1024;
|
|
pte = pde & ~( (page_size - 1) & ~0xfff); /* align to page_size */
|
|
} else {
|
|
/* 4 KB page */
|
|
pte_addr = ((pde & ~0xfff) + (((addr >> 12) & 0x1ff) << 3)) &
|
|
env->a20_mask;
|
|
page_size = 4096;
|
|
pte = ldl_phys(pte_addr);
|
|
}
|
|
} else {
|
|
if (!(env->cr[0] & CR0_PG_MASK)) {
|
|
pte = addr;
|
|
page_size = 4096;
|
|
} else {
|
|
/* page directory entry */
|
|
pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & env->a20_mask;
|
|
pde = ldl_phys(pde_addr);
|
|
if (!(pde & PG_PRESENT_MASK))
|
|
return -1;
|
|
if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
|
|
pte = pde & ~0x003ff000; /* align to 4MB */
|
|
page_size = 4096 * 1024;
|
|
} else {
|
|
/* page directory entry */
|
|
pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & env->a20_mask;
|
|
pte = ldl_phys(pte_addr);
|
|
if (!(pte & PG_PRESENT_MASK))
|
|
return -1;
|
|
page_size = 4096;
|
|
}
|
|
}
|
|
pte = pte & env->a20_mask;
|
|
}
|
|
|
|
page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
|
|
paddr = (pte & TARGET_PAGE_MASK) + page_offset;
|
|
return paddr;
|
|
}
|
|
#endif /* !CONFIG_USER_ONLY */
|
|
|
|
#if defined(USE_CODE_COPY)
|
|
struct fpstate {
|
|
uint16_t fpuc;
|
|
uint16_t dummy1;
|
|
uint16_t fpus;
|
|
uint16_t dummy2;
|
|
uint16_t fptag;
|
|
uint16_t dummy3;
|
|
|
|
uint32_t fpip;
|
|
uint32_t fpcs;
|
|
uint32_t fpoo;
|
|
uint32_t fpos;
|
|
uint8_t fpregs1[8 * 10];
|
|
};
|
|
|
|
void restore_native_fp_state(CPUState *env)
|
|
{
|
|
int fptag, i, j;
|
|
struct fpstate fp1, *fp = &fp1;
|
|
|
|
fp->fpuc = env->fpuc;
|
|
fp->fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
|
|
fptag = 0;
|
|
for (i=7; i>=0; i--) {
|
|
fptag <<= 2;
|
|
if (env->fptags[i]) {
|
|
fptag |= 3;
|
|
} else {
|
|
/* the FPU automatically computes it */
|
|
}
|
|
}
|
|
fp->fptag = fptag;
|
|
j = env->fpstt;
|
|
for(i = 0;i < 8; i++) {
|
|
memcpy(&fp->fpregs1[i * 10], &env->fpregs[j].d, 10);
|
|
j = (j + 1) & 7;
|
|
}
|
|
asm volatile ("frstor %0" : "=m" (*fp));
|
|
env->native_fp_regs = 1;
|
|
}
|
|
|
|
void save_native_fp_state(CPUState *env)
|
|
{
|
|
int fptag, i, j;
|
|
uint16_t fpuc;
|
|
struct fpstate fp1, *fp = &fp1;
|
|
|
|
asm volatile ("fsave %0" : : "m" (*fp));
|
|
env->fpuc = fp->fpuc;
|
|
env->fpstt = (fp->fpus >> 11) & 7;
|
|
env->fpus = fp->fpus & ~0x3800;
|
|
fptag = fp->fptag;
|
|
for(i = 0;i < 8; i++) {
|
|
env->fptags[i] = ((fptag & 3) == 3);
|
|
fptag >>= 2;
|
|
}
|
|
j = env->fpstt;
|
|
for(i = 0;i < 8; i++) {
|
|
memcpy(&env->fpregs[j].d, &fp->fpregs1[i * 10], 10);
|
|
j = (j + 1) & 7;
|
|
}
|
|
/* we must restore the default rounding state */
|
|
/* XXX: we do not restore the exception state */
|
|
fpuc = 0x037f | (env->fpuc & (3 << 10));
|
|
asm volatile("fldcw %0" : : "m" (fpuc));
|
|
env->native_fp_regs = 0;
|
|
}
|
|
#endif
|