qemu/target/riscv/insn_trans
Daniel Henrique Barboza 929e521a47 target/riscv: always clear vstart for ldst_whole insns
Commit 8ff8ac6329 added a conditional to guard the vext_ldst_whole()
helper if vstart >= evl. But by skipping the helper we're also not
setting vstart = 0 at the end of the insns, which is incorrect.

We'll move the conditional to vext_ldst_whole(), following in line with
the removal of all brconds vstart >= vl that the next patch will do. The
idea is to make the helpers responsible for their own vstart management.

Fix ldst_whole isns by:

- remove the brcond that skips the helper if vstart is >= evl;

- vext_ldst_whole() now does an early exit with the same check, where
  evl = (vlenb * nf) >> log2_esz, but the early exit will also clear
  vstart.

The 'width' param is now unneeded in ldst_whole_trans() and is also
removed. It was used for the evl calculation for the brcond and has no
other use now.  The 'width' is reflected in vext_ldst_whole() via
log2_esz, which is encoded by GEN_VEXT_LD_WHOLE() as
"ctzl(sizeof(ETYPE))".

Suggested-by: Max Chou <max.chou@sifive.com>
Fixes: 8ff8ac6329 ("target/riscv: rvv: Add missing early exit condition for whole register load/store")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Message-ID: <20240314175704.478276-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-03-22 15:18:28 +10:00
..
trans_privileged.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rva.c.inc RISC-V: Add support for Ztso 2024-03-08 19:47:48 +10:00
trans_rvb.c.inc target/riscv: Drop tcg_temp_free 2023-03-05 13:44:08 -08:00
trans_rvbf16.c.inc target/riscv/insn_trans/trans_rvbf16.c.inc: use cpu->cfg.vlenb 2024-02-09 20:43:14 +10:00
trans_rvd.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvf.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvh.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvi.c.inc RISC-V: Add support for Ztso 2024-03-08 19:47:48 +10:00
trans_rvk.c.inc target/riscv: Drop tcg_temp_free 2023-03-05 13:44:08 -08:00
trans_rvm.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvv.c.inc target/riscv: always clear vstart for ldst_whole insns 2024-03-22 15:18:28 +10:00
trans_rvvk.c.inc target/riscv/insn_trans/trans_rvvk.c.inc: use 'vlenb' 2024-02-09 20:43:14 +10:00
trans_rvzacas.c.inc target/riscv: Add support for Zacas extension 2024-01-10 18:47:47 +10:00
trans_rvzawrs.c.inc target/riscv: Change gen_set_pc_imm to gen_update_pc 2023-06-13 17:35:20 +10:00
trans_rvzce.c.inc target/riscv: Update $ra with current $pc in trans_cm_jalt() 2024-03-08 15:37:20 +10:00
trans_rvzfa.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvzfh.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvzicbo.c.inc target/riscv: rename ext_icboz to ext_zicboz 2023-11-07 11:02:17 +10:00
trans_rvzicond.c.inc target/riscv: refactor Zicond support 2023-05-05 10:49:50 +10:00
trans_svinval.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_xthead.c.inc target/riscv: Enable xtheadsync under user mode 2024-02-09 20:43:14 +10:00
trans_xventanacondops.c.inc target/riscv: redirect XVentanaCondOps to use the Zicond functions 2023-05-05 10:49:50 +10:00