928f0ce4e8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
209 lines
7.3 KiB
C
209 lines
7.3 KiB
C
/*
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* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HEXAGON_GEN_TCG_HVX_H
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#define HEXAGON_GEN_TCG_HVX_H
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/*
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* Histogram instructions
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*
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* Note that these instructions operate directly on the vector registers
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* and therefore happen after commit.
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*
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* The generate_<tag> function is called twice
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* The first time is during the normal TCG generation
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* ctx->pre_commit is true
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* In the masked cases, we save the mask to the qtmp temporary
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* Otherwise, there is nothing to do
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* The second call is at the end of gen_commit_packet
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* ctx->pre_commit is false
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* Generate the call to the helper
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*/
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static inline void assert_vhist_tmp(DisasContext *ctx)
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{
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/* vhist instructions require exactly one .tmp to be defined */
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g_assert(ctx->tmp_vregs_idx == 1);
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}
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#define fGEN_TCG_V6_vhist(SHORTCODE) \
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if (!ctx->pre_commit) { \
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assert_vhist_tmp(ctx); \
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gen_helper_vhist(cpu_env); \
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}
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#define fGEN_TCG_V6_vhistq(SHORTCODE) \
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do { \
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if (ctx->pre_commit) { \
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intptr_t dstoff = offsetof(CPUHexagonState, qtmp); \
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tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \
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sizeof(MMVector), sizeof(MMVector)); \
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} else { \
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assert_vhist_tmp(ctx); \
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gen_helper_vhistq(cpu_env); \
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} \
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} while (0)
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#define fGEN_TCG_V6_vwhist256(SHORTCODE) \
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if (!ctx->pre_commit) { \
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assert_vhist_tmp(ctx); \
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gen_helper_vwhist256(cpu_env); \
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}
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#define fGEN_TCG_V6_vwhist256q(SHORTCODE) \
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do { \
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if (ctx->pre_commit) { \
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intptr_t dstoff = offsetof(CPUHexagonState, qtmp); \
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tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \
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sizeof(MMVector), sizeof(MMVector)); \
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} else { \
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assert_vhist_tmp(ctx); \
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gen_helper_vwhist256q(cpu_env); \
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} \
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} while (0)
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#define fGEN_TCG_V6_vwhist256_sat(SHORTCODE) \
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if (!ctx->pre_commit) { \
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assert_vhist_tmp(ctx); \
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gen_helper_vwhist256_sat(cpu_env); \
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}
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#define fGEN_TCG_V6_vwhist256q_sat(SHORTCODE) \
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do { \
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if (ctx->pre_commit) { \
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intptr_t dstoff = offsetof(CPUHexagonState, qtmp); \
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tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \
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sizeof(MMVector), sizeof(MMVector)); \
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} else { \
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assert_vhist_tmp(ctx); \
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gen_helper_vwhist256q_sat(cpu_env); \
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} \
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} while (0)
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#define fGEN_TCG_V6_vwhist128(SHORTCODE) \
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if (!ctx->pre_commit) { \
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assert_vhist_tmp(ctx); \
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gen_helper_vwhist128(cpu_env); \
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}
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#define fGEN_TCG_V6_vwhist128q(SHORTCODE) \
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do { \
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if (ctx->pre_commit) { \
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intptr_t dstoff = offsetof(CPUHexagonState, qtmp); \
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tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \
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sizeof(MMVector), sizeof(MMVector)); \
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} else { \
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assert_vhist_tmp(ctx); \
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gen_helper_vwhist128q(cpu_env); \
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} \
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} while (0)
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#define fGEN_TCG_V6_vwhist128m(SHORTCODE) \
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if (!ctx->pre_commit) { \
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TCGv tcgv_uiV = tcg_constant_tl(uiV); \
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assert_vhist_tmp(ctx); \
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gen_helper_vwhist128m(cpu_env, tcgv_uiV); \
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}
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#define fGEN_TCG_V6_vwhist128qm(SHORTCODE) \
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do { \
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if (ctx->pre_commit) { \
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intptr_t dstoff = offsetof(CPUHexagonState, qtmp); \
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tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \
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sizeof(MMVector), sizeof(MMVector)); \
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} else { \
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TCGv tcgv_uiV = tcg_constant_tl(uiV); \
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assert_vhist_tmp(ctx); \
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gen_helper_vwhist128qm(cpu_env, tcgv_uiV); \
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} \
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} while (0)
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#define fGEN_TCG_V6_vassign(SHORTCODE) \
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tcg_gen_gvec_mov(MO_64, VdV_off, VuV_off, \
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sizeof(MMVector), sizeof(MMVector))
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/* Vector conditional move */
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#define fGEN_TCG_VEC_CMOV(PRED) \
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do { \
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TCGv lsb = tcg_temp_new(); \
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TCGLabel *false_label = gen_new_label(); \
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TCGLabel *end_label = gen_new_label(); \
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tcg_gen_andi_tl(lsb, PsV, 1); \
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tcg_gen_brcondi_tl(TCG_COND_NE, lsb, PRED, false_label); \
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tcg_temp_free(lsb); \
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tcg_gen_gvec_mov(MO_64, VdV_off, VuV_off, \
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sizeof(MMVector), sizeof(MMVector)); \
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tcg_gen_br(end_label); \
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gen_set_label(false_label); \
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tcg_gen_ori_tl(hex_slot_cancelled, hex_slot_cancelled, \
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1 << insn->slot); \
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gen_set_label(end_label); \
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} while (0)
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/* Vector conditional move (true) */
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#define fGEN_TCG_V6_vcmov(SHORTCODE) \
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fGEN_TCG_VEC_CMOV(1)
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/* Vector conditional move (false) */
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#define fGEN_TCG_V6_vncmov(SHORTCODE) \
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fGEN_TCG_VEC_CMOV(0)
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/* Vector add - various forms */
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#define fGEN_TCG_V6_vaddb(SHORTCODE) \
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tcg_gen_gvec_add(MO_8, VdV_off, VuV_off, VvV_off, \
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sizeof(MMVector), sizeof(MMVector))
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#define fGEN_TCG_V6_vaddh(SHORTCYDE) \
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tcg_gen_gvec_add(MO_16, VdV_off, VuV_off, VvV_off, \
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sizeof(MMVector), sizeof(MMVector))
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#define fGEN_TCG_V6_vaddw(SHORTCODE) \
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tcg_gen_gvec_add(MO_32, VdV_off, VuV_off, VvV_off, \
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sizeof(MMVector), sizeof(MMVector))
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#define fGEN_TCG_V6_vaddb_dv(SHORTCODE) \
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tcg_gen_gvec_add(MO_8, VddV_off, VuuV_off, VvvV_off, \
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sizeof(MMVector) * 2, sizeof(MMVector) * 2)
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#define fGEN_TCG_V6_vaddh_dv(SHORTCYDE) \
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tcg_gen_gvec_add(MO_16, VddV_off, VuuV_off, VvvV_off, \
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sizeof(MMVector) * 2, sizeof(MMVector) * 2)
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#define fGEN_TCG_V6_vaddw_dv(SHORTCODE) \
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tcg_gen_gvec_add(MO_32, VddV_off, VuuV_off, VvvV_off, \
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sizeof(MMVector) * 2, sizeof(MMVector) * 2)
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/* Vector sub - various forms */
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#define fGEN_TCG_V6_vsubb(SHORTCODE) \
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tcg_gen_gvec_sub(MO_8, VdV_off, VuV_off, VvV_off, \
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sizeof(MMVector), sizeof(MMVector))
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#define fGEN_TCG_V6_vsubh(SHORTCODE) \
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tcg_gen_gvec_sub(MO_16, VdV_off, VuV_off, VvV_off, \
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sizeof(MMVector), sizeof(MMVector))
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#define fGEN_TCG_V6_vsubw(SHORTCODE) \
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tcg_gen_gvec_sub(MO_32, VdV_off, VuV_off, VvV_off, \
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sizeof(MMVector), sizeof(MMVector))
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#define fGEN_TCG_V6_vsubb_dv(SHORTCODE) \
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tcg_gen_gvec_sub(MO_8, VddV_off, VuuV_off, VvvV_off, \
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sizeof(MMVector) * 2, sizeof(MMVector) * 2)
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#define fGEN_TCG_V6_vsubh_dv(SHORTCODE) \
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tcg_gen_gvec_sub(MO_16, VddV_off, VuuV_off, VvvV_off, \
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sizeof(MMVector) * 2, sizeof(MMVector) * 2)
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#define fGEN_TCG_V6_vsubw_dv(SHORTCODE) \
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tcg_gen_gvec_sub(MO_32, VddV_off, VuuV_off, VvvV_off, \
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sizeof(MMVector) * 2, sizeof(MMVector) * 2)
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#endif
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