Peter Maydell 91a358fdfb target/arm: Implement MVE VSUB, VMUL (scalar) ...

Implement the scalar forms of the MVE VSUB and VMUL insns.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-24-peter.maydell@linaro.org

2021-06-24 14:58:47 +01:00

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alpha

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arm

target/arm: Implement MVE VSUB, VMUL (scalar)

2021-06-24 14:58:47 +01:00

avr

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cris

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hexagon

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hppa

target/hppa: Remove unused 'memory.h' header

2021-06-05 21:23:14 +02:00

i386

x86 queue, 2021-06-18

2021-06-21 11:26:04 +01:00

m68k

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microblaze

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mips

target/mips: Fix 'Uncoditional' typo

2021-06-05 21:28:54 +02:00

nios2

target/nios2: fix page-fit instruction count

2021-06-05 21:17:10 +02:00

openrisc

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ppc

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riscv

target/riscv: rvb: add b-ext version cpu option

2021-06-08 09:59:46 +10:00

rx

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s390x

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sh4

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sparc

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tricore

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xtensa

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meson.build

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