6cc64796f2
The XIVE router base class currently inherits an empty realize hook from the sysbus device base class, but it will soon implement one of its own to perform some sanity checks. Do the preliminary plumbing to have it called. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191219181155.32530-6-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
99 lines
3.1 KiB
C
99 lines
3.1 KiB
C
/*
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* QEMU PowerPC sPAPR XIVE interrupt controller model
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*
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* Copyright (c) 2017-2018, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#ifndef PPC_SPAPR_XIVE_H
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#define PPC_SPAPR_XIVE_H
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#include "hw/ppc/spapr_irq.h"
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#include "hw/ppc/xive.h"
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#define TYPE_SPAPR_XIVE "spapr-xive"
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#define SPAPR_XIVE(obj) OBJECT_CHECK(SpaprXive, (obj), TYPE_SPAPR_XIVE)
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#define SPAPR_XIVE_CLASS(klass) \
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OBJECT_CLASS_CHECK(SpaprXiveClass, (klass), TYPE_SPAPR_XIVE)
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#define SPAPR_XIVE_GET_CLASS(obj) \
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OBJECT_GET_CLASS(SpaprXiveClass, (obj), TYPE_SPAPR_XIVE)
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typedef struct SpaprXive {
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XiveRouter parent;
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/* Internal interrupt source for IPIs and virtual devices */
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XiveSource source;
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hwaddr vc_base;
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/* END ESB MMIOs */
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XiveENDSource end_source;
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hwaddr end_base;
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/* DT */
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gchar *nodename;
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/* Routing table */
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XiveEAS *eat;
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uint32_t nr_irqs;
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XiveEND *endt;
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uint32_t nr_ends;
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/* TIMA mapping address */
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hwaddr tm_base;
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MemoryRegion tm_mmio;
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/* KVM support */
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int fd;
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void *tm_mmap;
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MemoryRegion tm_mmio_kvm;
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VMChangeStateEntry *change;
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} SpaprXive;
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typedef struct SpaprXiveClass {
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XiveRouterClass parent;
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DeviceRealize parent_realize;
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} SpaprXiveClass;
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/*
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* The sPAPR machine has a unique XIVE IC device. Assign a fixed value
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* to the controller block id value. It can nevertheless be changed
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* for testing purpose.
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*/
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#define SPAPR_XIVE_BLOCK_ID 0x0
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void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon);
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void spapr_xive_hcall_init(SpaprMachineState *spapr);
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void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable);
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void spapr_xive_map_mmio(SpaprXive *xive);
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int spapr_xive_end_to_target(uint8_t end_blk, uint32_t end_idx,
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uint32_t *out_server, uint8_t *out_prio);
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/*
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* KVM XIVE device helpers
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*/
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int kvmppc_xive_connect(SpaprInterruptController *intc, uint32_t nr_servers,
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Error **errp);
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void kvmppc_xive_disconnect(SpaprInterruptController *intc);
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void kvmppc_xive_reset(SpaprXive *xive, Error **errp);
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void kvmppc_xive_set_source_config(SpaprXive *xive, uint32_t lisn, XiveEAS *eas,
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Error **errp);
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void kvmppc_xive_sync_source(SpaprXive *xive, uint32_t lisn, Error **errp);
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uint64_t kvmppc_xive_esb_rw(XiveSource *xsrc, int srcno, uint32_t offset,
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uint64_t data, bool write);
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void kvmppc_xive_set_queue_config(SpaprXive *xive, uint8_t end_blk,
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uint32_t end_idx, XiveEND *end,
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Error **errp);
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void kvmppc_xive_get_queue_config(SpaprXive *xive, uint8_t end_blk,
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uint32_t end_idx, XiveEND *end,
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Error **errp);
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void kvmppc_xive_synchronize_state(SpaprXive *xive, Error **errp);
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int kvmppc_xive_pre_save(SpaprXive *xive);
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int kvmppc_xive_post_load(SpaprXive *xive, int version_id);
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#endif /* PPC_SPAPR_XIVE_H */
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