qemu/target/loongarch/insn_trans
Song Gao 65bfaaae6a
target/loongarch: Fix the vinsgr2vr/vpickve2gr instructions cause system coredump
The vinsgr2vr/vpickve2gr instructions need use get_src/get_dst to get
gpr registers value, not cpu_gpr[]. The $zero register does not
have cpu_gpr[0] allocated.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1662

Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230525120005.2223413-1-gaosong@loongson.cn>
2023-05-26 17:21:16 +08:00
..
trans_arith.c.inc target/loongarch: Drop tcg_temp_free 2023-03-05 13:44:07 -08:00
trans_atomic.c.inc target/loongarch: Drop tcg_temp_free 2023-03-05 13:44:07 -08:00
trans_bit.c.inc target/loongarch: Drop tcg_temp_free 2023-03-05 13:44:07 -08:00
trans_branch.c.inc target/loongarch: Disassemble jirl properly 2023-01-23 15:36:36 -10:00
trans_extra.c.inc target/loongarch: Add timer related instructions support. 2022-06-06 18:09:03 +00:00
trans_farith.c.inc target/loongarch: Use {set/get}_gpr replace to cpu_fpr 2023-05-06 11:19:50 +08:00
trans_fcmp.c.inc target/loongarch: Use {set/get}_gpr replace to cpu_fpr 2023-05-06 11:19:50 +08:00
trans_fcnv.c.inc target/loongarch: Add floating point conversion instruction translation 2022-06-06 18:09:03 +00:00
trans_fmemory.c.inc target/loongarch: Use {set/get}_gpr replace to cpu_fpr 2023-05-06 11:19:50 +08:00
trans_fmov.c.inc target/loongarch: Use {set/get}_gpr replace to cpu_fpr 2023-05-06 11:19:50 +08:00
trans_lsx.c.inc target/loongarch: Fix the vinsgr2vr/vpickve2gr instructions cause system coredump 2023-05-26 17:21:16 +08:00
trans_memory.c.inc target/loongarch: Drop tcg_temp_free 2023-03-05 13:44:07 -08:00
trans_privileged.c.inc target/loongarch: Drop tcg_temp_free 2023-03-05 13:44:07 -08:00
trans_shift.c.inc target/loongarch: Drop tcg_temp_free 2023-03-05 13:44:07 -08:00