3a977deebe
This change introduces emulation for the Intel 82576 adapter, AKA igb. The details of the device will be provided by the documentation that will follow this change. This initial implementation of igb does not cover the full feature set, but it selectively implements changes necessary to pass tests of Linut Test Project, and Windows HLK. The below is the list of the implemented changes; anything not listed here is not implemented: New features: - igb advanced descriptor handling - Support of 16 queues - SRRCTL.BSIZEPACKET register field - SRRCTL.RDMTS register field - Tx descriptor completion writeback - Extended RA registers - VMDq feature - MRQC "Multiple Receive Queues Enable" register field - DTXSWC.Loopback_en register field - VMOLR.ROMPE register field - VMOLR.AUPE register field - VLVF.VLAN_id register field - VLVF.VI_En register field - VF - Mailbox - Reset - Extended interrupt registers - Default values for IGP01E1000 PHY registers Removed features: - e1000e extended descriptor - e1000e packet split descriptor - Legacy descriptor - PHY register paging - MAC Registers - Legacy interrupt timer registers - Legacy EEPROM registers - PBA/POEM registers - RSRPD register - RFCTL.ACKDIS - RCTL.DTYPE - Copper PHY registers Misc: - VET register format - ICR register format Signed-off-by: Gal Hammer <gal.hammer@sap.com> Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> [Jason: don't abort on msi(x)_init()] Signed-off-by: Jason Wang <jasowang@redhat.com>
624 lines
17 KiB
C
624 lines
17 KiB
C
/*
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* QEMU Intel 82576 SR/IOV Ethernet Controller Emulation
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*
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* Datasheet:
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* https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/82576eg-gbe-datasheet.pdf
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*
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* Copyright (c) 2020-2023 Red Hat, Inc.
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* Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
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* Developed by Daynix Computing LTD (http://www.daynix.com)
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*
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* Authors:
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* Akihiko Odaki <akihiko.odaki@daynix.com>
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* Gal Hammmer <gal.hammer@sap.com>
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* Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
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* Dmitry Fleytman <dmitry@daynix.com>
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* Leonid Bloch <leonid@daynix.com>
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* Yan Vugenfirer <yan@daynix.com>
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*
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* Based on work done by:
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* Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
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* Copyright (c) 2008 Qumranet
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* Based on work done by:
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* Copyright (c) 2007 Dan Aloni
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* Copyright (c) 2004 Antony T Curtis
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "net/eth.h"
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#include "net/net.h"
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#include "net/tap.h"
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#include "qemu/module.h"
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#include "qemu/range.h"
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#include "sysemu/sysemu.h"
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#include "hw/hw.h"
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#include "hw/net/mii.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pcie.h"
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#include "hw/pci/pcie_sriov.h"
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#include "hw/pci/msi.h"
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#include "hw/pci/msix.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "igb_common.h"
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#include "igb_core.h"
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#include "trace.h"
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#include "qapi/error.h"
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#include "qom/object.h"
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#define TYPE_IGB "igb"
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OBJECT_DECLARE_SIMPLE_TYPE(IGBState, IGB)
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struct IGBState {
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PCIDevice parent_obj;
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NICState *nic;
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NICConf conf;
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MemoryRegion mmio;
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MemoryRegion flash;
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MemoryRegion io;
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MemoryRegion msix;
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uint32_t ioaddr;
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IGBCore core;
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};
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#define IGB_CAP_SRIOV_OFFSET (0x160)
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#define IGB_VF_OFFSET (0x80)
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#define IGB_VF_STRIDE (2)
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#define E1000E_MMIO_IDX 0
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#define E1000E_FLASH_IDX 1
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#define E1000E_IO_IDX 2
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#define E1000E_MSIX_IDX 3
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#define E1000E_MMIO_SIZE (128 * KiB)
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#define E1000E_FLASH_SIZE (128 * KiB)
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#define E1000E_IO_SIZE (32)
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#define E1000E_MSIX_SIZE (16 * KiB)
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static void igb_write_config(PCIDevice *dev, uint32_t addr,
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uint32_t val, int len)
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{
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IGBState *s = IGB(dev);
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trace_igb_write_config(addr, val, len);
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pci_default_write_config(dev, addr, val, len);
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if (range_covers_byte(addr, len, PCI_COMMAND) &&
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(dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) {
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igb_start_recv(&s->core);
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}
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}
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uint64_t
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igb_mmio_read(void *opaque, hwaddr addr, unsigned size)
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{
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IGBState *s = opaque;
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return igb_core_read(&s->core, addr, size);
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}
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void
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igb_mmio_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
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{
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IGBState *s = opaque;
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igb_core_write(&s->core, addr, val, size);
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}
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static bool
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igb_io_get_reg_index(IGBState *s, uint32_t *idx)
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{
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if (s->ioaddr < 0x1FFFF) {
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*idx = s->ioaddr;
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return true;
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}
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if (s->ioaddr < 0x7FFFF) {
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trace_e1000e_wrn_io_addr_undefined(s->ioaddr);
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return false;
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}
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if (s->ioaddr < 0xFFFFF) {
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trace_e1000e_wrn_io_addr_flash(s->ioaddr);
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return false;
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}
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trace_e1000e_wrn_io_addr_unknown(s->ioaddr);
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return false;
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}
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static uint64_t
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igb_io_read(void *opaque, hwaddr addr, unsigned size)
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{
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IGBState *s = opaque;
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uint32_t idx = 0;
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uint64_t val;
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switch (addr) {
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case E1000_IOADDR:
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trace_e1000e_io_read_addr(s->ioaddr);
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return s->ioaddr;
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case E1000_IODATA:
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if (igb_io_get_reg_index(s, &idx)) {
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val = igb_core_read(&s->core, idx, sizeof(val));
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trace_e1000e_io_read_data(idx, val);
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return val;
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}
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return 0;
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default:
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trace_e1000e_wrn_io_read_unknown(addr);
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return 0;
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}
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}
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static void
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igb_io_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
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{
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IGBState *s = opaque;
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uint32_t idx = 0;
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switch (addr) {
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case E1000_IOADDR:
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trace_e1000e_io_write_addr(val);
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s->ioaddr = (uint32_t) val;
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return;
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case E1000_IODATA:
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if (igb_io_get_reg_index(s, &idx)) {
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trace_e1000e_io_write_data(idx, val);
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igb_core_write(&s->core, idx, val, sizeof(val));
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}
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return;
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default:
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trace_e1000e_wrn_io_write_unknown(addr);
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return;
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}
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}
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static const MemoryRegionOps mmio_ops = {
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.read = igb_mmio_read,
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.write = igb_mmio_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static const MemoryRegionOps io_ops = {
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.read = igb_io_read,
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.write = igb_io_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static bool
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igb_nc_can_receive(NetClientState *nc)
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{
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IGBState *s = qemu_get_nic_opaque(nc);
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return igb_can_receive(&s->core);
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}
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static ssize_t
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igb_nc_receive_iov(NetClientState *nc, const struct iovec *iov, int iovcnt)
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{
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IGBState *s = qemu_get_nic_opaque(nc);
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return igb_receive_iov(&s->core, iov, iovcnt);
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}
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static ssize_t
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igb_nc_receive(NetClientState *nc, const uint8_t *buf, size_t size)
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{
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IGBState *s = qemu_get_nic_opaque(nc);
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return igb_receive(&s->core, buf, size);
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}
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static void
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igb_set_link_status(NetClientState *nc)
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{
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IGBState *s = qemu_get_nic_opaque(nc);
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igb_core_set_link_status(&s->core);
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}
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static NetClientInfo net_igb_info = {
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.type = NET_CLIENT_DRIVER_NIC,
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.size = sizeof(NICState),
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.can_receive = igb_nc_can_receive,
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.receive = igb_nc_receive,
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.receive_iov = igb_nc_receive_iov,
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.link_status_changed = igb_set_link_status,
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};
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/*
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* EEPROM (NVM) contents documented in section 6.1, table 6-1:
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* and in 6.10 Software accessed words.
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*/
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static const uint16_t igb_eeprom_template[] = {
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/* Address |Compat.|OEM sp.| ImRev | OEM sp. */
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0x0000, 0x0000, 0x0000, 0x0d34, 0xffff, 0x2010, 0xffff, 0xffff,
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/* PBA |ICtrl1 | SSID | SVID | DevID |-------|ICtrl2 */
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0x1040, 0xffff, 0x002b, 0x0000, 0x8086, 0x10c9, 0x0000, 0x70c3,
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/* SwPin0| DevID | EESZ |-------|ICtrl3 |PCI-tc | MSIX | APtr */
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0x0004, 0x10c9, 0x5c00, 0x0000, 0x2880, 0x0014, 0x4a40, 0x0060,
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/* PCIe Init. Conf 1,2,3 |PCICtrl| LD1,3 |DDevID |DevRev | LD0,2 */
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0x6cfb, 0xc7b0, 0x0abe, 0x0403, 0x0783, 0x10a6, 0x0001, 0x0602,
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/* SwPin1| FunC |LAN-PWR|ManHwC |ICtrl3 | IOVct |VDevID |-------*/
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0x0004, 0x0020, 0x0000, 0x004a, 0x2080, 0x00f5, 0x10ca, 0x0000,
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/*---------------| LD1,3 | LD0,2 | ROEnd | ROSta | Wdog | VPD */
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0x0000, 0x0000, 0x4784, 0x4602, 0x0000, 0x0000, 0x1000, 0xffff,
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/* PCSet0| Ccfg0 |PXEver |IBAcap |PCSet1 | Ccfg1 |iSCVer | ?? */
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0x0100, 0x4000, 0x131f, 0x4013, 0x0100, 0x4000, 0xffff, 0xffff,
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/* PCSet2| Ccfg2 |PCSet3 | Ccfg3 | ?? |AltMacP| ?? |CHKSUM */
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0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x00e0, 0xffff, 0x0000,
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/* NC-SIC */
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0x0003,
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};
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static void igb_core_realize(IGBState *s)
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{
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s->core.owner = &s->parent_obj;
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s->core.owner_nic = s->nic;
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}
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static void
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igb_init_msix(IGBState *s)
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{
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int i, res;
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res = msix_init(PCI_DEVICE(s), IGB_MSIX_VEC_NUM,
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&s->msix,
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E1000E_MSIX_IDX, 0,
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&s->msix,
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E1000E_MSIX_IDX, 0x2000,
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0x70, NULL);
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if (res < 0) {
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trace_e1000e_msix_init_fail(res);
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} else {
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for (i = 0; i < IGB_MSIX_VEC_NUM; i++) {
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msix_vector_use(PCI_DEVICE(s), i);
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}
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}
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}
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static void
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igb_cleanup_msix(IGBState *s)
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{
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msix_unuse_all_vectors(PCI_DEVICE(s));
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msix_uninit(PCI_DEVICE(s), &s->msix, &s->msix);
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}
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static void
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igb_init_net_peer(IGBState *s, PCIDevice *pci_dev, uint8_t *macaddr)
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{
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DeviceState *dev = DEVICE(pci_dev);
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NetClientState *nc;
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int i;
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s->nic = qemu_new_nic(&net_igb_info, &s->conf,
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object_get_typename(OBJECT(s)), dev->id, s);
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s->core.max_queue_num = s->conf.peers.queues ? s->conf.peers.queues - 1 : 0;
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trace_e1000e_mac_set_permanent(MAC_ARG(macaddr));
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memcpy(s->core.permanent_mac, macaddr, sizeof(s->core.permanent_mac));
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qemu_format_nic_info_str(qemu_get_queue(s->nic), macaddr);
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/* Setup virtio headers */
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for (i = 0; i < s->conf.peers.queues; i++) {
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nc = qemu_get_subqueue(s->nic, i);
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if (!nc->peer || !qemu_has_vnet_hdr(nc->peer)) {
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trace_e1000e_cfg_support_virtio(false);
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return;
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}
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}
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trace_e1000e_cfg_support_virtio(true);
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s->core.has_vnet = true;
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for (i = 0; i < s->conf.peers.queues; i++) {
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nc = qemu_get_subqueue(s->nic, i);
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qemu_set_vnet_hdr_len(nc->peer, sizeof(struct virtio_net_hdr));
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qemu_using_vnet_hdr(nc->peer, true);
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}
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}
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static int
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igb_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc)
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{
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Error *local_err = NULL;
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int ret = pci_add_capability(pdev, PCI_CAP_ID_PM, offset,
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PCI_PM_SIZEOF, &local_err);
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if (local_err) {
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error_report_err(local_err);
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return ret;
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}
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pci_set_word(pdev->config + offset + PCI_PM_PMC,
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PCI_PM_CAP_VER_1_1 |
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pmc);
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pci_set_word(pdev->wmask + offset + PCI_PM_CTRL,
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PCI_PM_CTRL_STATE_MASK |
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PCI_PM_CTRL_PME_ENABLE |
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PCI_PM_CTRL_DATA_SEL_MASK);
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pci_set_word(pdev->w1cmask + offset + PCI_PM_CTRL,
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PCI_PM_CTRL_PME_STATUS);
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return ret;
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}
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static void igb_pci_realize(PCIDevice *pci_dev, Error **errp)
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{
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IGBState *s = IGB(pci_dev);
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uint8_t *macaddr;
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int ret;
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trace_e1000e_cb_pci_realize();
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pci_dev->config_write = igb_write_config;
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pci_dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
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pci_dev->config[PCI_INTERRUPT_PIN] = 1;
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/* Define IO/MMIO regions */
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memory_region_init_io(&s->mmio, OBJECT(s), &mmio_ops, s,
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"igb-mmio", E1000E_MMIO_SIZE);
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pci_register_bar(pci_dev, E1000E_MMIO_IDX,
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PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio);
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/*
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* We provide a dummy implementation for the flash BAR
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* for drivers that may theoretically probe for its presence.
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*/
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memory_region_init(&s->flash, OBJECT(s),
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"igb-flash", E1000E_FLASH_SIZE);
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pci_register_bar(pci_dev, E1000E_FLASH_IDX,
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PCI_BASE_ADDRESS_SPACE_MEMORY, &s->flash);
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memory_region_init_io(&s->io, OBJECT(s), &io_ops, s,
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"igb-io", E1000E_IO_SIZE);
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pci_register_bar(pci_dev, E1000E_IO_IDX,
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PCI_BASE_ADDRESS_SPACE_IO, &s->io);
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memory_region_init(&s->msix, OBJECT(s), "igb-msix",
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E1000E_MSIX_SIZE);
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pci_register_bar(pci_dev, E1000E_MSIX_IDX,
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PCI_BASE_ADDRESS_MEM_TYPE_64, &s->msix);
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/* Create networking backend */
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qemu_macaddr_default_if_unset(&s->conf.macaddr);
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macaddr = s->conf.macaddr.a;
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/* Add PCI capabilities in reverse order */
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assert(pcie_endpoint_cap_init(pci_dev, 0xa0) > 0);
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igb_init_msix(s);
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ret = msi_init(pci_dev, 0x50, 1, true, true, NULL);
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if (ret) {
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trace_e1000e_msi_init_fail(ret);
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}
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if (igb_add_pm_capability(pci_dev, 0x40, PCI_PM_CAP_DSI) < 0) {
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hw_error("Failed to initialize PM capability");
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}
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/* PCIe extended capabilities (in order) */
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if (pcie_aer_init(pci_dev, 1, 0x100, 0x40, errp) < 0) {
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hw_error("Failed to initialize AER capability");
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}
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pcie_ari_init(pci_dev, 0x150, 1);
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pcie_sriov_pf_init(pci_dev, IGB_CAP_SRIOV_OFFSET, "igbvf",
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IGB_82576_VF_DEV_ID, IGB_MAX_VF_FUNCTIONS, IGB_MAX_VF_FUNCTIONS,
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IGB_VF_OFFSET, IGB_VF_STRIDE);
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pcie_sriov_pf_init_vf_bar(pci_dev, 0,
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PCI_BASE_ADDRESS_MEM_TYPE_64 | PCI_BASE_ADDRESS_MEM_PREFETCH,
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16 * KiB);
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pcie_sriov_pf_init_vf_bar(pci_dev, 3,
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|
PCI_BASE_ADDRESS_MEM_TYPE_64 | PCI_BASE_ADDRESS_MEM_PREFETCH,
|
|
16 * KiB);
|
|
|
|
igb_init_net_peer(s, pci_dev, macaddr);
|
|
|
|
/* Initialize core */
|
|
igb_core_realize(s);
|
|
|
|
igb_core_pci_realize(&s->core,
|
|
igb_eeprom_template,
|
|
sizeof(igb_eeprom_template),
|
|
macaddr);
|
|
}
|
|
|
|
static void igb_pci_uninit(PCIDevice *pci_dev)
|
|
{
|
|
IGBState *s = IGB(pci_dev);
|
|
|
|
trace_e1000e_cb_pci_uninit();
|
|
|
|
igb_core_pci_uninit(&s->core);
|
|
|
|
pcie_sriov_pf_exit(pci_dev);
|
|
pcie_cap_exit(pci_dev);
|
|
|
|
qemu_del_nic(s->nic);
|
|
|
|
igb_cleanup_msix(s);
|
|
msi_uninit(pci_dev);
|
|
}
|
|
|
|
static void igb_qdev_reset_hold(Object *obj)
|
|
{
|
|
PCIDevice *d = PCI_DEVICE(obj);
|
|
IGBState *s = IGB(obj);
|
|
|
|
trace_e1000e_cb_qdev_reset_hold();
|
|
|
|
pcie_sriov_pf_disable_vfs(d);
|
|
igb_core_reset(&s->core);
|
|
}
|
|
|
|
static int igb_pre_save(void *opaque)
|
|
{
|
|
IGBState *s = opaque;
|
|
|
|
trace_e1000e_cb_pre_save();
|
|
|
|
igb_core_pre_save(&s->core);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int igb_post_load(void *opaque, int version_id)
|
|
{
|
|
IGBState *s = opaque;
|
|
|
|
trace_e1000e_cb_post_load();
|
|
return igb_core_post_load(&s->core);
|
|
}
|
|
|
|
static const VMStateDescription igb_vmstate_tx = {
|
|
.name = "igb-tx",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT16(vlan, struct igb_tx),
|
|
VMSTATE_UINT16(mss, struct igb_tx),
|
|
VMSTATE_BOOL(tse, struct igb_tx),
|
|
VMSTATE_BOOL(ixsm, struct igb_tx),
|
|
VMSTATE_BOOL(txsm, struct igb_tx),
|
|
VMSTATE_BOOL(first, struct igb_tx),
|
|
VMSTATE_BOOL(skip_cp, struct igb_tx),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static const VMStateDescription igb_vmstate_intr_timer = {
|
|
.name = "igb-intr-timer",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_TIMER_PTR(timer, IGBIntrDelayTimer),
|
|
VMSTATE_BOOL(running, IGBIntrDelayTimer),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
#define VMSTATE_IGB_INTR_DELAY_TIMER(_f, _s) \
|
|
VMSTATE_STRUCT(_f, _s, 0, \
|
|
igb_vmstate_intr_timer, IGBIntrDelayTimer)
|
|
|
|
#define VMSTATE_IGB_INTR_DELAY_TIMER_ARRAY(_f, _s, _num) \
|
|
VMSTATE_STRUCT_ARRAY(_f, _s, _num, 0, \
|
|
igb_vmstate_intr_timer, IGBIntrDelayTimer)
|
|
|
|
static const VMStateDescription igb_vmstate = {
|
|
.name = "igb",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.pre_save = igb_pre_save,
|
|
.post_load = igb_post_load,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_PCI_DEVICE(parent_obj, IGBState),
|
|
VMSTATE_MSIX(parent_obj, IGBState),
|
|
|
|
VMSTATE_UINT32(ioaddr, IGBState),
|
|
VMSTATE_UINT8(core.rx_desc_len, IGBState),
|
|
VMSTATE_UINT16_ARRAY(core.eeprom, IGBState, IGB_EEPROM_SIZE),
|
|
VMSTATE_UINT16_ARRAY(core.phy, IGBState, MAX_PHY_REG_ADDRESS + 1),
|
|
VMSTATE_UINT32_ARRAY(core.mac, IGBState, E1000E_MAC_SIZE),
|
|
VMSTATE_UINT8_ARRAY(core.permanent_mac, IGBState, ETH_ALEN),
|
|
|
|
VMSTATE_IGB_INTR_DELAY_TIMER_ARRAY(core.eitr, IGBState,
|
|
IGB_INTR_NUM),
|
|
|
|
VMSTATE_UINT32_ARRAY(core.eitr_guest_value, IGBState, IGB_INTR_NUM),
|
|
|
|
VMSTATE_STRUCT_ARRAY(core.tx, IGBState, IGB_NUM_QUEUES, 0,
|
|
igb_vmstate_tx, struct igb_tx),
|
|
|
|
VMSTATE_INT64(core.timadj, IGBState),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static Property igb_properties[] = {
|
|
DEFINE_NIC_PROPERTIES(IGBState, conf),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void igb_class_init(ObjectClass *class, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(class);
|
|
ResettableClass *rc = RESETTABLE_CLASS(class);
|
|
PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
|
|
|
|
c->realize = igb_pci_realize;
|
|
c->exit = igb_pci_uninit;
|
|
c->vendor_id = PCI_VENDOR_ID_INTEL;
|
|
c->device_id = E1000_DEV_ID_82576;
|
|
c->revision = 1;
|
|
c->class_id = PCI_CLASS_NETWORK_ETHERNET;
|
|
|
|
rc->phases.hold = igb_qdev_reset_hold;
|
|
|
|
dc->desc = "Intel 82576 Gigabit Ethernet Controller";
|
|
dc->vmsd = &igb_vmstate;
|
|
|
|
device_class_set_props(dc, igb_properties);
|
|
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
|
|
}
|
|
|
|
static void igb_instance_init(Object *obj)
|
|
{
|
|
IGBState *s = IGB(obj);
|
|
device_add_bootindex_property(obj, &s->conf.bootindex,
|
|
"bootindex", "/ethernet-phy@0",
|
|
DEVICE(obj));
|
|
}
|
|
|
|
static const TypeInfo igb_info = {
|
|
.name = TYPE_IGB,
|
|
.parent = TYPE_PCI_DEVICE,
|
|
.instance_size = sizeof(IGBState),
|
|
.class_init = igb_class_init,
|
|
.instance_init = igb_instance_init,
|
|
.interfaces = (InterfaceInfo[]) {
|
|
{ INTERFACE_PCIE_DEVICE },
|
|
{ }
|
|
},
|
|
};
|
|
|
|
static void igb_register_types(void)
|
|
{
|
|
type_register_static(&igb_info);
|
|
}
|
|
|
|
type_init(igb_register_types)
|