132b475a73
The IoTKit doesn't have any MSCs itself but it does need some wiring to connect the external signals from MSCs in the outer board model up to the registers and the NVIC IRQ line. We also need to expose a MemoryRegion corresponding to the AHB bus, so that MSCs in the outer board model can use that as their downstream port. (In the FPGA this is the "AHB Slave Expansion" ports shown in the block diagram in the AN505 documentation.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180820141116.9118-14-peter.maydell@linaro.org Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
137 lines
4.3 KiB
C
137 lines
4.3 KiB
C
/*
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* ARM IoT Kit
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*
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* Copyright (c) 2018 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/* This is a model of the Arm IoT Kit which is documented in
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* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
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* It contains:
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* a Cortex-M33
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* the IDAU
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* some timers and watchdogs
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* two peripheral protection controllers
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* a memory protection controller
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* a security controller
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* a bus fabric which arranges that some parts of the address
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* space are secure and non-secure aliases of each other
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*
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* QEMU interface:
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* + QOM property "memory" is a MemoryRegion containing the devices provided
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* by the board model.
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* + QOM property "MAINCLK" is the frequency of the main system clock
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* + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts
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* + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts, which
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* are wired to the NVIC lines 32 .. n+32
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* + sysbus MMIO region 0 is the "AHB Slave Expansion" which allows
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* bus master devices in the board model to make transactions into
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* all the devices and memory areas in the IoTKit
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* Controlling up to 4 AHB expansion PPBs which a system using the IoTKit
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* might provide:
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* + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15]
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* + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15]
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* + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable
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* + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear
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* + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status
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* Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit
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* might provide:
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* + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15]
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* + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15]
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* + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable
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* + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear
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* + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status
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* Controlling each of the 16 expansion MPCs which a system using the IoTKit
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* might provide:
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* + named GPIO inputs mpcexp_status[0..15]
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* Controlling each of the 16 expansion MSCs which a system using the IoTKit
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* might provide:
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* + named GPIO inputs mscexp_status[0..15]
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* + named GPIO outputs mscexp_clear[0..15]
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* + named GPIO outputs mscexp_ns[0..15]
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*/
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#ifndef IOTKIT_H
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#define IOTKIT_H
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#include "hw/sysbus.h"
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#include "hw/arm/armv7m.h"
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#include "hw/misc/iotkit-secctl.h"
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#include "hw/misc/tz-ppc.h"
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#include "hw/misc/tz-mpc.h"
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#include "hw/timer/cmsdk-apb-timer.h"
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#include "hw/timer/cmsdk-apb-dualtimer.h"
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#include "hw/watchdog/cmsdk-apb-watchdog.h"
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#include "hw/misc/iotkit-sysctl.h"
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#include "hw/misc/iotkit-sysinfo.h"
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#include "hw/or-irq.h"
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#include "hw/core/split-irq.h"
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#define TYPE_IOTKIT "iotkit"
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#define IOTKIT(obj) OBJECT_CHECK(IoTKit, (obj), TYPE_IOTKIT)
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/* We have an IRQ splitter and an OR gate input for each external PPC
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* and the 2 internal PPCs
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*/
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#define NUM_EXTERNAL_PPCS (IOTS_NUM_AHB_EXP_PPC + IOTS_NUM_APB_EXP_PPC)
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#define NUM_PPCS (NUM_EXTERNAL_PPCS + 2)
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typedef struct IoTKit {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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ARMv7MState armv7m;
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IoTKitSecCtl secctl;
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TZPPC apb_ppc0;
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TZPPC apb_ppc1;
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TZMPC mpc;
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CMSDKAPBTIMER timer0;
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CMSDKAPBTIMER timer1;
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CMSDKAPBTIMER s32ktimer;
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qemu_or_irq ppc_irq_orgate;
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SplitIRQ sec_resp_splitter;
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SplitIRQ ppc_irq_splitter[NUM_PPCS];
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SplitIRQ mpc_irq_splitter[IOTS_NUM_EXP_MPC + IOTS_NUM_MPC];
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qemu_or_irq mpc_irq_orgate;
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qemu_or_irq nmi_orgate;
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CMSDKAPBDualTimer dualtimer;
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CMSDKAPBWatchdog s32kwatchdog;
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CMSDKAPBWatchdog nswatchdog;
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CMSDKAPBWatchdog swatchdog;
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IoTKitSysCtl sysctl;
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IoTKitSysCtl sysinfo;
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MemoryRegion container;
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MemoryRegion alias1;
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MemoryRegion alias2;
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MemoryRegion alias3;
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MemoryRegion sram0;
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qemu_irq *exp_irqs;
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qemu_irq ppc0_irq;
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qemu_irq ppc1_irq;
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qemu_irq sec_resp_cfg;
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qemu_irq sec_resp_cfg_in;
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qemu_irq nsc_cfg_in;
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qemu_irq irq_status_in[NUM_EXTERNAL_PPCS];
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qemu_irq mpcexp_status_in[IOTS_NUM_EXP_MPC];
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uint32_t nsccfg;
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/* Properties */
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MemoryRegion *board_memory;
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uint32_t exp_numirq;
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uint32_t mainclk_frq;
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} IoTKit;
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#endif
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