qemu/include/hw/ppc
Cédric Le Goater 8f09231631 ppc/pnv: Introduce PBA registers
The PBA bridge unit (Power Bus Access) connects the OCC (On Chip
Controller) to the Power bus and System Memory. The PBA is used to
gather sensor data, for power management, for sleep states, for
initial boot, among other things.

The PBA logic provides a set of four registers PowerBus Access Base
Address Registers (PBABAR0..3) which map the OCC address space to the
PowerBus space. These registers are setup by the initial FW and define
the PowerBus Range of system memory that can be accessed by PBA.

The current modeling of the PBABAR registers is done under the common
XSCOM handlers. We introduce a specific XSCOM regions for these
registers and fix :

 - BAR sizes and BAR masks
 - The mapping of the OCC common area. It is common to all chips and
   should be mapped once.  We will address per-OCC area in the next
   change.
 - OCC common area is in BAR 3 on P8

Inspired by previous work of Balamuruhan S <bala24@linux.ibm.com>

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191211082912.2625-2-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17 10:39:48 +11:00
..
fdt.h target/ppc: Pass cpu instead of env to ppc_create_page_sizes_prop() 2018-04-27 18:05:22 +10:00
mac_dbdma.h mac_dbdma: remove DBDMA_init() function 2017-09-27 13:05:41 +10:00
openpic_kvm.h openpic: move KVM-specific declarations into separate openpic_kvm.h file 2018-03-06 13:16:29 +11:00
openpic.h hw/core: Move cpu.c, cpu.h from qom/ to hw/core/ 2019-08-21 13:24:01 +02:00
pnv_core.h ppc/pnv: Add a PnvChip pointer to PnvCore 2019-10-24 13:33:33 +11:00
pnv_homer.h ppc/pnv: Introduce PBA registers 2019-12-17 10:39:48 +11:00
pnv_lpc.h ppc/pnv: add a LPC Controller model for POWER10 2019-12-17 10:39:48 +11:00
pnv_occ.h hw/ppc/pnv_occ: add sram device model for occ common area 2019-10-04 10:25:23 +10:00
pnv_pnor.h ppc/pnv: Add HIOMAP commands 2019-12-17 10:39:47 +11:00
pnv_psi.h ppc/pnv: add a PSI bridge model for POWER10 2019-12-17 10:39:48 +11:00
pnv_xive.h ppc/pnv: Introduce a pnv_xive_block_id() helper 2019-12-17 10:39:48 +11:00
pnv_xscom.h ppc/pnv: Introduce PBA registers 2019-12-17 10:39:48 +11:00
pnv.h ppc/pnv: Introduce PBA registers 2019-12-17 10:39:48 +11:00
ppc4xx.h Clean up inclusion of exec/cpu-common.h 2019-08-16 13:31:52 +02:00
ppc_e500.h intc/openpic: Build openpic only once 2013-07-09 21:33:02 +02:00
ppc.h target/ppc: Work [S]PURR implementation and add HV support 2019-12-17 10:39:48 +11:00
spapr_cpu_core.h spapr: Implement H_PROD 2019-08-21 17:17:12 +10:00
spapr_drc.h sysemu: Split sysemu/runstate.h off sysemu/sysemu.h 2019-08-16 13:37:36 +02:00
spapr_irq.h spapr: Pass the maximum number of vCPUs to the KVM interrupt controller 2019-12-17 10:39:48 +11:00
spapr_ovec.h spapr: Simplify ovec diff 2019-12-17 10:39:48 +11:00
spapr_rtas.h tests: add RTAS command in the protocol 2016-09-23 10:29:40 +10:00
spapr_tpm_proxy.h spapr: initial implementation for H_TPM_COMM/spapr-tpm-proxy 2019-08-21 17:17:12 +10:00
spapr_vio.h spapr: Replace spapr_vio_qirq() helper with spapr_vio_irq_pulse() helper 2019-10-04 19:08:22 +10:00
spapr_xive.h spapr: Pass the maximum number of vCPUs to the KVM interrupt controller 2019-12-17 10:39:48 +11:00
spapr.h spapr: Fold h_cas_compose_response() into h_client_architecture_support() 2019-12-17 10:39:48 +11:00
xics_spapr.h spapr: Pass the maximum number of vCPUs to the KVM interrupt controller 2019-12-17 10:39:48 +11:00
xics.h ppc: Add intc_destroy() handlers to SpaprInterruptController/PnvChip 2019-11-18 11:49:11 +01:00
xive_regs.h ppc/pnv: Dump the XIVE NVT table 2019-12-17 10:39:48 +11:00
xive.h ppc/pnv: Extend XiveRouter with a get_block_id() handler 2019-12-17 10:39:48 +11:00