8b758d0568
Fix for rndrashift_short_acc to set correct value to higher 64 bits. This change also corrects conditions when bit 23 of the DSPControl register is set. The existing test files have been extended with several examples that trigger the issues. One bug/example in the test file for EXTR_RS_W has been found and reported by Klaus Peichl. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
118 lines
2.3 KiB
C
118 lines
2.3 KiB
C
#include<stdio.h>
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#include<assert.h>
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int main()
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{
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int rt, ach, acl, dsp;
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int result;
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ach = 0x05;
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acl = 0xB4CB;
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result = 0x7FFFFFFF;
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__asm
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("mthi %2, $ac1\n\t"
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"mtlo %3, $ac1\n\t"
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"extr_rs.w %0, $ac1, 0x03\n\t"
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"rddsp %1\n\t"
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: "=r"(rt), "=r"(dsp)
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: "r"(ach), "r"(acl)
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);
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dsp = (dsp >> 23) & 0x01;
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assert(dsp == 1);
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assert(result == rt);
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/* Clear dspcontrol */
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dsp = 0;
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__asm
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("wrdsp %0\n\t"
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:
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: "r"(dsp)
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);
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ach = 0x01;
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acl = 0xB4CB;
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result = 0x10000B4D;
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__asm
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("mthi %2, $ac1\n\t"
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"mtlo %3, $ac1\n\t"
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"extr_rs.w %0, $ac1, 0x04\n\t"
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"rddsp %1\n\t"
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: "=r"(rt), "=r"(dsp)
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: "r"(ach), "r"(acl)
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);
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dsp = (dsp >> 23) & 0x01;
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assert(dsp == 0);
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assert(result == rt);
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/* Clear dspcontrol */
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dsp = 0;
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__asm
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("wrdsp %0\n\t"
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:
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: "r"(dsp)
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);
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ach = 0x3fffffff;
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acl = 0x2bcdef01;
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result = 0x7ffffffe;
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__asm
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("mthi %2, $ac1\n\t"
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"mtlo %3, $ac1\n\t"
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"extr_rs.w %0, $ac1, 0x1F\n\t"
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"rddsp %1\n\t"
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: "=r"(rt), "=r"(dsp)
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: "r"(ach), "r"(acl)
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);
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dsp = (dsp >> 23) & 0x01;
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assert(dsp == 0);
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assert(result == rt);
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/* Clear dspcontrol */
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dsp = 0;
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__asm
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("wrdsp %0\n\t"
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:
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: "r"(dsp)
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);
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ach = 0x80000000;
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acl = 0x00000000;
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result = 0x80000000;
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__asm
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("mthi %2, $ac1\n\t"
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"mtlo %3, $ac1\n\t"
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"extr_rs.w %0, $ac1, 0x1F\n\t"
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"rddsp %1\n\t"
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: "=r"(rt), "=r"(dsp)
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: "r"(ach), "r"(acl)
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);
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dsp = (dsp >> 23) & 0x01;
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assert(dsp == 1);
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assert(result == rt);
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/* Clear dspcontrol */
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dsp = 0;
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__asm
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("wrdsp %0\n\t"
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:
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: "r"(dsp)
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);
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ach = 0xFFFFFFFF;
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acl = 0xFFFFFFFF;
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result = 0;
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__asm
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("mthi %2, $ac1\n\t"
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"mtlo %3, $ac1\n\t"
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"extr_rs.w %0, $ac1, 0x1F\n\t"
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"rddsp %1\n\t"
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: "=r"(rt), "=r"(dsp)
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: "r"(ach), "r"(acl)
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);
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dsp = (dsp >> 23) & 0x01;
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assert(dsp == 0);
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assert(result == rt);
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return 0;
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}
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