Jim Wilson 8e73df6aa3

RISC-V: Fixes to CSR_* register macros. ...

This adds some missing CSR_* register macros, and documents some as being
priv v1.9.1 specific.

Signed-off-by: Jim Wilson <jimw@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20190212230830.9160-1-jimw@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

2019-03-19 05:13:24 -07:00

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alpha

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arm

target/arm: Check access permission to ADDVL/ADDPL/RDVL

2019-03-15 11:12:29 +00:00

cris

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hppa

target/hppa: Avoid squishing DISAS_IAQ_N_STALE_EXIT

2019-03-15 10:09:55 -07:00

i386

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lm32

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m68k

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microblaze

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mips

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moxie

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nios2

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openrisc

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ppc

spapr: Use CamelCase properly

2019-03-12 14:33:05 +11:00

riscv

RISC-V: Fixes to CSR_* register macros.

2019-03-19 05:13:24 -07:00

s390x

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sh4

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sparc

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tilegx

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tricore

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unicore32

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xtensa

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