ec150c7e09
Back in 2016, we discussed[1] rules for headers, and these were
generally liked:
1. Have a carefully curated header that's included everywhere first. We
got that already thanks to Peter: osdep.h.
2. Headers should normally include everything they need beyond osdep.h.
If exceptions are needed for some reason, they must be documented in
the header. If all that's needed from a header is typedefs, put
those into qemu/typedefs.h instead of including the header.
3. Cyclic inclusion is forbidden.
This patch gets include/ closer to obeying 2.
It's actually extracted from my "[RFC] Baby steps towards saner
headers" series[2], which demonstrates a possible path towards
checking 2 automatically. It passes the RFC test there.
[1] Message-ID: <87h9g8j57d.fsf@blackfin.pond.sub.org>
https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg03345.html
[2] Message-Id: <20190711122827.18970-1-armbru@redhat.com>
https://lists.nongnu.org/archive/html/qemu-devel/2019-07/msg02715.html
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20190812052359.30071-2-armbru@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
138 lines
4.7 KiB
C
138 lines
4.7 KiB
C
/*
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* Samsung exynos4210 SoC emulation
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
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* Maksim Kozlov <m.kozlov@samsung.com>
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* Evgeny Voevodin <e.voevodin@samsung.com>
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* Igor Mitsyanko <i.mitsyanko@samsung.com>
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef EXYNOS4210_H
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#define EXYNOS4210_H
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#include "hw/sysbus.h"
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#include "target/arm/cpu-qom.h"
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#define EXYNOS4210_NCPUS 2
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#define EXYNOS4210_DRAM0_BASE_ADDR 0x40000000
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#define EXYNOS4210_DRAM1_BASE_ADDR 0xa0000000
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#define EXYNOS4210_DRAM_MAX_SIZE 0x60000000 /* 1.5 GB */
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#define EXYNOS4210_IROM_BASE_ADDR 0x00000000
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#define EXYNOS4210_IROM_SIZE 0x00010000 /* 64 KB */
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#define EXYNOS4210_IROM_MIRROR_BASE_ADDR 0x02000000
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#define EXYNOS4210_IROM_MIRROR_SIZE 0x00010000 /* 64 KB */
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#define EXYNOS4210_IRAM_BASE_ADDR 0x02020000
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#define EXYNOS4210_IRAM_SIZE 0x00020000 /* 128 KB */
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/* Secondary CPU startup code is in IROM memory */
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#define EXYNOS4210_SMP_BOOT_ADDR EXYNOS4210_IROM_BASE_ADDR
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#define EXYNOS4210_SMP_BOOT_SIZE 0x1000
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#define EXYNOS4210_BASE_BOOT_ADDR EXYNOS4210_DRAM0_BASE_ADDR
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/* Secondary CPU polling address to get loader start from */
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#define EXYNOS4210_SECOND_CPU_BOOTREG 0x10020814
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#define EXYNOS4210_SMP_PRIVATE_BASE_ADDR 0x10500000
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#define EXYNOS4210_L2X0_BASE_ADDR 0x10502000
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/*
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* exynos4210 IRQ subsystem stub definitions.
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*/
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#define EXYNOS4210_IRQ_GATE_NINPUTS 2 /* Internal and External GIC */
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#define EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ 64
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#define EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ 16
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#define EXYNOS4210_MAX_INT_COMBINER_IN_IRQ \
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(EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ * 8)
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#define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ \
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(EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8)
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#define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit) ((grp)*8 + (bit))
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#define EXYNOS4210_COMBINER_GET_GRP_NUM(irq) ((irq) / 8)
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#define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \
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((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq))
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/* IRQs number for external and internal GIC */
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#define EXYNOS4210_EXT_GIC_NIRQ (160-32)
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#define EXYNOS4210_INT_GIC_NIRQ 64
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#define EXYNOS4210_I2C_NUMBER 9
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typedef struct Exynos4210Irq {
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qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
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qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
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qemu_irq int_gic_irq[EXYNOS4210_INT_GIC_NIRQ];
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qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ];
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qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
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} Exynos4210Irq;
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typedef struct Exynos4210State {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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ARMCPU *cpu[EXYNOS4210_NCPUS];
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Exynos4210Irq irqs;
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qemu_irq *irq_table;
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MemoryRegion chipid_mem;
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MemoryRegion iram_mem;
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MemoryRegion irom_mem;
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MemoryRegion irom_alias_mem;
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MemoryRegion boot_secondary;
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MemoryRegion bootreg_mem;
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I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
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} Exynos4210State;
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#define TYPE_EXYNOS4210_SOC "exynos4210"
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#define EXYNOS4210_SOC(obj) \
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OBJECT_CHECK(Exynos4210State, obj, TYPE_EXYNOS4210_SOC)
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void exynos4210_write_secondary(ARMCPU *cpu,
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const struct arm_boot_info *info);
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/* Initialize exynos4210 IRQ subsystem stub */
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qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
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/* Initialize board IRQs.
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* These IRQs contain splitted Int/External Combiner and External Gic IRQs */
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void exynos4210_init_board_irqs(Exynos4210Irq *s);
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/* Get IRQ number from exynos4210 IRQ subsystem stub.
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* To identify IRQ source use internal combiner group and bit number
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* grp - group number
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* bit - bit number inside group */
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uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit);
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/*
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* Get Combiner input GPIO into irqs structure
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*/
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void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev,
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int ext);
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/*
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* exynos4210 UART
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*/
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DeviceState *exynos4210_uart_create(hwaddr addr,
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int fifo_size,
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int channel,
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Chardev *chr,
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qemu_irq irq);
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#endif /* EXYNOS4210_H */
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