8da4f8f7b7
This is not useful and will be in the way for support of user created PHB4 devices. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20211213132830.108372-13-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
625 lines
21 KiB
C
625 lines
21 KiB
C
/*
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* QEMU PowerPC PowerNV (POWER9) PHB4 model
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*
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* Copyright (c) 2018-2020, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu-common.h"
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#include "qemu/log.h"
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#include "target/ppc/cpu.h"
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#include "hw/ppc/fdt.h"
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#include "hw/pci-host/pnv_phb4_regs.h"
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#include "hw/pci-host/pnv_phb4.h"
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#include "hw/ppc/pnv_xscom.h"
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#include "hw/pci/pci_bridge.h"
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#include "hw/pci/pci_bus.h"
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#include "hw/ppc/pnv.h"
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#include "hw/qdev-properties.h"
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#include <libfdt.h>
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#define phb_pec_error(pec, fmt, ...) \
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qemu_log_mask(LOG_GUEST_ERROR, "phb4_pec[%d:%d]: " fmt "\n", \
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(pec)->chip_id, (pec)->index, ## __VA_ARGS__)
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static uint64_t pnv_pec_nest_xscom_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque);
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uint32_t reg = addr >> 3;
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/* TODO: add list of allowed registers and error out if not */
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return pec->nest_regs[reg];
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}
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static void pnv_pec_nest_xscom_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque);
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uint32_t reg = addr >> 3;
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switch (reg) {
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case PEC_NEST_PBCQ_HW_CONFIG:
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case PEC_NEST_DROP_PRIO_CTRL:
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case PEC_NEST_PBCQ_ERR_INJECT:
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case PEC_NEST_PCI_NEST_CLK_TRACE_CTL:
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case PEC_NEST_PBCQ_PMON_CTRL:
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case PEC_NEST_PBCQ_PBUS_ADDR_EXT:
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case PEC_NEST_PBCQ_PRED_VEC_TIMEOUT:
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case PEC_NEST_CAPP_CTRL:
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case PEC_NEST_PBCQ_READ_STK_OVR:
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case PEC_NEST_PBCQ_WRITE_STK_OVR:
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case PEC_NEST_PBCQ_STORE_STK_OVR:
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case PEC_NEST_PBCQ_RETRY_BKOFF_CTRL:
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pec->nest_regs[reg] = val;
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break;
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default:
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phb_pec_error(pec, "%s @0x%"HWADDR_PRIx"=%"PRIx64"\n", __func__,
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addr, val);
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}
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}
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static const MemoryRegionOps pnv_pec_nest_xscom_ops = {
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.read = pnv_pec_nest_xscom_read,
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.write = pnv_pec_nest_xscom_write,
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.valid.min_access_size = 8,
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.valid.max_access_size = 8,
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.impl.min_access_size = 8,
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.impl.max_access_size = 8,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static uint64_t pnv_pec_pci_xscom_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque);
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uint32_t reg = addr >> 3;
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/* TODO: add list of allowed registers and error out if not */
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return pec->pci_regs[reg];
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}
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static void pnv_pec_pci_xscom_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque);
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uint32_t reg = addr >> 3;
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switch (reg) {
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case PEC_PCI_PBAIB_HW_CONFIG:
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case PEC_PCI_PBAIB_READ_STK_OVR:
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pec->pci_regs[reg] = val;
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break;
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default:
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phb_pec_error(pec, "%s @0x%"HWADDR_PRIx"=%"PRIx64"\n", __func__,
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addr, val);
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}
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}
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static const MemoryRegionOps pnv_pec_pci_xscom_ops = {
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.read = pnv_pec_pci_xscom_read,
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.write = pnv_pec_pci_xscom_write,
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.valid.min_access_size = 8,
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.valid.max_access_size = 8,
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.impl.min_access_size = 8,
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.impl.max_access_size = 8,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static uint64_t pnv_pec_stk_nest_xscom_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(opaque);
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uint32_t reg = addr >> 3;
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/* TODO: add list of allowed registers and error out if not */
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return stack->nest_regs[reg];
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}
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static void pnv_pec_stk_update_map(PnvPhb4PecStack *stack)
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{
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PnvPhb4PecState *pec = stack->pec;
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MemoryRegion *sysmem = get_system_memory();
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uint64_t bar_en = stack->nest_regs[PEC_NEST_STK_BAR_EN];
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uint64_t bar, mask, size;
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char name[64];
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/*
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* NOTE: This will really not work well if those are remapped
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* after the PHB has created its sub regions. We could do better
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* if we had a way to resize regions but we don't really care
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* that much in practice as the stuff below really only happens
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* once early during boot
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*/
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/* Handle unmaps */
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if (memory_region_is_mapped(&stack->mmbar0) &&
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!(bar_en & PEC_NEST_STK_BAR_EN_MMIO0)) {
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memory_region_del_subregion(sysmem, &stack->mmbar0);
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}
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if (memory_region_is_mapped(&stack->mmbar1) &&
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!(bar_en & PEC_NEST_STK_BAR_EN_MMIO1)) {
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memory_region_del_subregion(sysmem, &stack->mmbar1);
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}
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if (memory_region_is_mapped(&stack->phbbar) &&
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!(bar_en & PEC_NEST_STK_BAR_EN_PHB)) {
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memory_region_del_subregion(sysmem, &stack->phbbar);
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}
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if (memory_region_is_mapped(&stack->intbar) &&
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!(bar_en & PEC_NEST_STK_BAR_EN_INT)) {
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memory_region_del_subregion(sysmem, &stack->intbar);
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}
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/* Update PHB */
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pnv_phb4_update_regions(stack);
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/* Handle maps */
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if (!memory_region_is_mapped(&stack->mmbar0) &&
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(bar_en & PEC_NEST_STK_BAR_EN_MMIO0)) {
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bar = stack->nest_regs[PEC_NEST_STK_MMIO_BAR0] >> 8;
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mask = stack->nest_regs[PEC_NEST_STK_MMIO_BAR0_MASK];
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size = ((~mask) >> 8) + 1;
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snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-mmio0",
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pec->chip_id, pec->index, stack->stack_no);
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memory_region_init(&stack->mmbar0, OBJECT(stack), name, size);
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memory_region_add_subregion(sysmem, bar, &stack->mmbar0);
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stack->mmio0_base = bar;
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stack->mmio0_size = size;
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}
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if (!memory_region_is_mapped(&stack->mmbar1) &&
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(bar_en & PEC_NEST_STK_BAR_EN_MMIO1)) {
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bar = stack->nest_regs[PEC_NEST_STK_MMIO_BAR1] >> 8;
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mask = stack->nest_regs[PEC_NEST_STK_MMIO_BAR1_MASK];
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size = ((~mask) >> 8) + 1;
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snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-mmio1",
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pec->chip_id, pec->index, stack->stack_no);
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memory_region_init(&stack->mmbar1, OBJECT(stack), name, size);
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memory_region_add_subregion(sysmem, bar, &stack->mmbar1);
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stack->mmio1_base = bar;
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stack->mmio1_size = size;
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}
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if (!memory_region_is_mapped(&stack->phbbar) &&
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(bar_en & PEC_NEST_STK_BAR_EN_PHB)) {
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bar = stack->nest_regs[PEC_NEST_STK_PHB_REGS_BAR] >> 8;
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size = PNV_PHB4_NUM_REGS << 3;
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snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-phb",
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pec->chip_id, pec->index, stack->stack_no);
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memory_region_init(&stack->phbbar, OBJECT(stack), name, size);
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memory_region_add_subregion(sysmem, bar, &stack->phbbar);
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}
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if (!memory_region_is_mapped(&stack->intbar) &&
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(bar_en & PEC_NEST_STK_BAR_EN_INT)) {
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bar = stack->nest_regs[PEC_NEST_STK_INT_BAR] >> 8;
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size = PNV_PHB4_MAX_INTs << 16;
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snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-int",
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stack->pec->chip_id, stack->pec->index, stack->stack_no);
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memory_region_init(&stack->intbar, OBJECT(stack), name, size);
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memory_region_add_subregion(sysmem, bar, &stack->intbar);
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}
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/* Update PHB */
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pnv_phb4_update_regions(stack);
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}
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static void pnv_pec_stk_nest_xscom_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(opaque);
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PnvPhb4PecState *pec = stack->pec;
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uint32_t reg = addr >> 3;
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switch (reg) {
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case PEC_NEST_STK_PCI_NEST_FIR:
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stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] = val;
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break;
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case PEC_NEST_STK_PCI_NEST_FIR_CLR:
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stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] &= val;
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break;
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case PEC_NEST_STK_PCI_NEST_FIR_SET:
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stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] |= val;
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break;
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case PEC_NEST_STK_PCI_NEST_FIR_MSK:
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stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] = val;
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break;
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case PEC_NEST_STK_PCI_NEST_FIR_MSKC:
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stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] &= val;
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break;
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case PEC_NEST_STK_PCI_NEST_FIR_MSKS:
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stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] |= val;
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break;
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case PEC_NEST_STK_PCI_NEST_FIR_ACT0:
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case PEC_NEST_STK_PCI_NEST_FIR_ACT1:
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stack->nest_regs[reg] = val;
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break;
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case PEC_NEST_STK_PCI_NEST_FIR_WOF:
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stack->nest_regs[reg] = 0;
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break;
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case PEC_NEST_STK_ERR_REPORT_0:
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case PEC_NEST_STK_ERR_REPORT_1:
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case PEC_NEST_STK_PBCQ_GNRL_STATUS:
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/* Flag error ? */
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break;
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case PEC_NEST_STK_PBCQ_MODE:
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stack->nest_regs[reg] = val & 0xff00000000000000ull;
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break;
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case PEC_NEST_STK_MMIO_BAR0:
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case PEC_NEST_STK_MMIO_BAR0_MASK:
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case PEC_NEST_STK_MMIO_BAR1:
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case PEC_NEST_STK_MMIO_BAR1_MASK:
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if (stack->nest_regs[PEC_NEST_STK_BAR_EN] &
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(PEC_NEST_STK_BAR_EN_MMIO0 |
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PEC_NEST_STK_BAR_EN_MMIO1)) {
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phb_pec_error(pec, "Changing enabled BAR unsupported\n");
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}
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stack->nest_regs[reg] = val & 0xffffffffff000000ull;
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break;
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case PEC_NEST_STK_PHB_REGS_BAR:
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if (stack->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_PHB) {
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phb_pec_error(pec, "Changing enabled BAR unsupported\n");
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}
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stack->nest_regs[reg] = val & 0xffffffffffc00000ull;
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break;
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case PEC_NEST_STK_INT_BAR:
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if (stack->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_INT) {
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phb_pec_error(pec, "Changing enabled BAR unsupported\n");
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}
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stack->nest_regs[reg] = val & 0xfffffff000000000ull;
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break;
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case PEC_NEST_STK_BAR_EN:
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stack->nest_regs[reg] = val & 0xf000000000000000ull;
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pnv_pec_stk_update_map(stack);
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break;
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case PEC_NEST_STK_DATA_FRZ_TYPE:
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case PEC_NEST_STK_PBCQ_TUN_BAR:
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/* Not used for now */
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stack->nest_regs[reg] = val;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "phb4_pec: nest_xscom_write 0x%"HWADDR_PRIx
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"=%"PRIx64"\n", addr, val);
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}
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}
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static const MemoryRegionOps pnv_pec_stk_nest_xscom_ops = {
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.read = pnv_pec_stk_nest_xscom_read,
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.write = pnv_pec_stk_nest_xscom_write,
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.valid.min_access_size = 8,
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.valid.max_access_size = 8,
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.impl.min_access_size = 8,
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.impl.max_access_size = 8,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static uint64_t pnv_pec_stk_pci_xscom_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(opaque);
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uint32_t reg = addr >> 3;
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/* TODO: add list of allowed registers and error out if not */
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return stack->pci_regs[reg];
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}
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static void pnv_pec_stk_pci_xscom_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(opaque);
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uint32_t reg = addr >> 3;
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switch (reg) {
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case PEC_PCI_STK_PCI_FIR:
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stack->nest_regs[reg] = val;
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break;
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case PEC_PCI_STK_PCI_FIR_CLR:
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stack->nest_regs[PEC_PCI_STK_PCI_FIR] &= val;
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break;
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case PEC_PCI_STK_PCI_FIR_SET:
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stack->nest_regs[PEC_PCI_STK_PCI_FIR] |= val;
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break;
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case PEC_PCI_STK_PCI_FIR_MSK:
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stack->nest_regs[reg] = val;
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break;
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case PEC_PCI_STK_PCI_FIR_MSKC:
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stack->nest_regs[PEC_PCI_STK_PCI_FIR_MSK] &= val;
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break;
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case PEC_PCI_STK_PCI_FIR_MSKS:
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stack->nest_regs[PEC_PCI_STK_PCI_FIR_MSK] |= val;
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break;
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case PEC_PCI_STK_PCI_FIR_ACT0:
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case PEC_PCI_STK_PCI_FIR_ACT1:
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stack->nest_regs[reg] = val;
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break;
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case PEC_PCI_STK_PCI_FIR_WOF:
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stack->nest_regs[reg] = 0;
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break;
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case PEC_PCI_STK_ETU_RESET:
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stack->nest_regs[reg] = val & 0x8000000000000000ull;
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/* TODO: Implement reset */
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break;
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case PEC_PCI_STK_PBAIB_ERR_REPORT:
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break;
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case PEC_PCI_STK_PBAIB_TX_CMD_CRED:
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case PEC_PCI_STK_PBAIB_TX_DAT_CRED:
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stack->nest_regs[reg] = val;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "phb4_pec_stk: pci_xscom_write 0x%"HWADDR_PRIx
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"=%"PRIx64"\n", addr, val);
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}
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}
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static const MemoryRegionOps pnv_pec_stk_pci_xscom_ops = {
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.read = pnv_pec_stk_pci_xscom_read,
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.write = pnv_pec_stk_pci_xscom_write,
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.valid.min_access_size = 8,
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.valid.max_access_size = 8,
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.impl.min_access_size = 8,
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.impl.max_access_size = 8,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static void pnv_pec_instance_init(Object *obj)
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{
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PnvPhb4PecState *pec = PNV_PHB4_PEC(obj);
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int i;
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for (i = 0; i < PHB4_PEC_MAX_STACKS; i++) {
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object_initialize_child(obj, "stack[*]", &pec->stacks[i],
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TYPE_PNV_PHB4_PEC_STACK);
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}
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}
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static int pnv_pec_phb_offset(PnvPhb4PecState *pec)
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{
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PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
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int index = pec->index;
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int offset = 0;
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while (index--) {
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offset += pecc->num_stacks[index];
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}
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return offset;
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}
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static void pnv_pec_realize(DeviceState *dev, Error **errp)
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{
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PnvPhb4PecState *pec = PNV_PHB4_PEC(dev);
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PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
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char name[64];
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int i;
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if (pec->index >= PNV_CHIP_GET_CLASS(pec->chip)->num_pecs) {
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error_setg(errp, "invalid PEC index: %d", pec->index);
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return;
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}
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pec->num_stacks = pecc->num_stacks[pec->index];
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/* Create stacks */
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for (i = 0; i < pec->num_stacks; i++) {
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PnvPhb4PecStack *stack = &pec->stacks[i];
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Object *stk_obj = OBJECT(stack);
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int phb_id = pnv_pec_phb_offset(pec) + i;
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|
|
|
object_property_set_int(stk_obj, "stack-no", i, &error_abort);
|
|
object_property_set_int(stk_obj, "phb-id", phb_id, &error_abort);
|
|
object_property_set_link(stk_obj, "pec", OBJECT(pec), &error_abort);
|
|
if (!qdev_realize(DEVICE(stk_obj), NULL, errp)) {
|
|
return;
|
|
}
|
|
}
|
|
for (; i < PHB4_PEC_MAX_STACKS; i++) {
|
|
object_unparent(OBJECT(&pec->stacks[i]));
|
|
}
|
|
|
|
/* Initialize the XSCOM regions for the PEC registers */
|
|
snprintf(name, sizeof(name), "xscom-pec-%d.%d-nest", pec->chip_id,
|
|
pec->index);
|
|
pnv_xscom_region_init(&pec->nest_regs_mr, OBJECT(dev),
|
|
&pnv_pec_nest_xscom_ops, pec, name,
|
|
PHB4_PEC_NEST_REGS_COUNT);
|
|
|
|
snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci", pec->chip_id,
|
|
pec->index);
|
|
pnv_xscom_region_init(&pec->pci_regs_mr, OBJECT(dev),
|
|
&pnv_pec_pci_xscom_ops, pec, name,
|
|
PHB4_PEC_PCI_REGS_COUNT);
|
|
}
|
|
|
|
static int pnv_pec_dt_xscom(PnvXScomInterface *dev, void *fdt,
|
|
int xscom_offset)
|
|
{
|
|
PnvPhb4PecState *pec = PNV_PHB4_PEC(dev);
|
|
PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(dev);
|
|
uint32_t nbase = pecc->xscom_nest_base(pec);
|
|
uint32_t pbase = pecc->xscom_pci_base(pec);
|
|
int offset, i;
|
|
char *name;
|
|
uint32_t reg[] = {
|
|
cpu_to_be32(nbase),
|
|
cpu_to_be32(pecc->xscom_nest_size),
|
|
cpu_to_be32(pbase),
|
|
cpu_to_be32(pecc->xscom_pci_size),
|
|
};
|
|
|
|
name = g_strdup_printf("pbcq@%x", nbase);
|
|
offset = fdt_add_subnode(fdt, xscom_offset, name);
|
|
_FDT(offset);
|
|
g_free(name);
|
|
|
|
_FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
|
|
|
|
_FDT((fdt_setprop_cell(fdt, offset, "ibm,pec-index", pec->index)));
|
|
_FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 1)));
|
|
_FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 0)));
|
|
_FDT((fdt_setprop(fdt, offset, "compatible", pecc->compat,
|
|
pecc->compat_size)));
|
|
|
|
for (i = 0; i < pec->num_stacks; i++) {
|
|
PnvPhb4PecStack *stack = &pec->stacks[i];
|
|
PnvPHB4 *phb = &stack->phb;
|
|
int stk_offset;
|
|
|
|
name = g_strdup_printf("stack@%x", i);
|
|
stk_offset = fdt_add_subnode(fdt, offset, name);
|
|
_FDT(stk_offset);
|
|
g_free(name);
|
|
_FDT((fdt_setprop(fdt, stk_offset, "compatible", pecc->stk_compat,
|
|
pecc->stk_compat_size)));
|
|
_FDT((fdt_setprop_cell(fdt, stk_offset, "reg", i)));
|
|
_FDT((fdt_setprop_cell(fdt, stk_offset, "ibm,phb-index", phb->phb_id)));
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static Property pnv_pec_properties[] = {
|
|
DEFINE_PROP_UINT32("index", PnvPhb4PecState, index, 0),
|
|
DEFINE_PROP_UINT32("chip-id", PnvPhb4PecState, chip_id, 0),
|
|
DEFINE_PROP_LINK("chip", PnvPhb4PecState, chip, TYPE_PNV_CHIP,
|
|
PnvChip *),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static uint32_t pnv_pec_xscom_pci_base(PnvPhb4PecState *pec)
|
|
{
|
|
return PNV9_XSCOM_PEC_PCI_BASE + 0x1000000 * pec->index;
|
|
}
|
|
|
|
static uint32_t pnv_pec_xscom_nest_base(PnvPhb4PecState *pec)
|
|
{
|
|
return PNV9_XSCOM_PEC_NEST_BASE + 0x400 * pec->index;
|
|
}
|
|
|
|
/*
|
|
* PEC0 -> 1 stack
|
|
* PEC1 -> 2 stacks
|
|
* PEC2 -> 3 stacks
|
|
*/
|
|
static const uint32_t pnv_pec_num_stacks[] = { 1, 2, 3 };
|
|
|
|
static void pnv_pec_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
|
|
PnvPhb4PecClass *pecc = PNV_PHB4_PEC_CLASS(klass);
|
|
static const char compat[] = "ibm,power9-pbcq";
|
|
static const char stk_compat[] = "ibm,power9-phb-stack";
|
|
|
|
xdc->dt_xscom = pnv_pec_dt_xscom;
|
|
|
|
dc->realize = pnv_pec_realize;
|
|
device_class_set_props(dc, pnv_pec_properties);
|
|
dc->user_creatable = false;
|
|
|
|
pecc->xscom_nest_base = pnv_pec_xscom_nest_base;
|
|
pecc->xscom_pci_base = pnv_pec_xscom_pci_base;
|
|
pecc->xscom_nest_size = PNV9_XSCOM_PEC_NEST_SIZE;
|
|
pecc->xscom_pci_size = PNV9_XSCOM_PEC_PCI_SIZE;
|
|
pecc->compat = compat;
|
|
pecc->compat_size = sizeof(compat);
|
|
pecc->stk_compat = stk_compat;
|
|
pecc->stk_compat_size = sizeof(stk_compat);
|
|
pecc->version = PNV_PHB4_VERSION;
|
|
pecc->device_id = PNV_PHB4_DEVICE_ID;
|
|
pecc->num_stacks = pnv_pec_num_stacks;
|
|
}
|
|
|
|
static const TypeInfo pnv_pec_type_info = {
|
|
.name = TYPE_PNV_PHB4_PEC,
|
|
.parent = TYPE_DEVICE,
|
|
.instance_size = sizeof(PnvPhb4PecState),
|
|
.instance_init = pnv_pec_instance_init,
|
|
.class_init = pnv_pec_class_init,
|
|
.class_size = sizeof(PnvPhb4PecClass),
|
|
.interfaces = (InterfaceInfo[]) {
|
|
{ TYPE_PNV_XSCOM_INTERFACE },
|
|
{ }
|
|
}
|
|
};
|
|
|
|
static void pnv_pec_stk_instance_init(Object *obj)
|
|
{
|
|
PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(obj);
|
|
|
|
object_initialize_child(obj, "phb", &stack->phb, TYPE_PNV_PHB4);
|
|
object_property_add_alias(obj, "phb-id", OBJECT(&stack->phb), "index");
|
|
}
|
|
|
|
static void pnv_pec_stk_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(dev);
|
|
PnvPhb4PecState *pec = stack->pec;
|
|
char name[64];
|
|
|
|
assert(pec);
|
|
|
|
/* Initialize the XSCOM regions for the stack registers */
|
|
snprintf(name, sizeof(name), "xscom-pec-%d.%d-nest-stack-%d",
|
|
pec->chip_id, pec->index, stack->stack_no);
|
|
pnv_xscom_region_init(&stack->nest_regs_mr, OBJECT(stack),
|
|
&pnv_pec_stk_nest_xscom_ops, stack, name,
|
|
PHB4_PEC_NEST_STK_REGS_COUNT);
|
|
|
|
snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-stack-%d",
|
|
pec->chip_id, pec->index, stack->stack_no);
|
|
pnv_xscom_region_init(&stack->pci_regs_mr, OBJECT(stack),
|
|
&pnv_pec_stk_pci_xscom_ops, stack, name,
|
|
PHB4_PEC_PCI_STK_REGS_COUNT);
|
|
|
|
/* PHB pass-through */
|
|
snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-stack-%d-phb",
|
|
pec->chip_id, pec->index, stack->stack_no);
|
|
pnv_xscom_region_init(&stack->phb_regs_mr, OBJECT(&stack->phb),
|
|
&pnv_phb4_xscom_ops, &stack->phb, name, 0x40);
|
|
|
|
/*
|
|
* Let the machine/chip realize the PHB object to customize more
|
|
* easily some fields
|
|
*/
|
|
}
|
|
|
|
static Property pnv_pec_stk_properties[] = {
|
|
DEFINE_PROP_UINT32("stack-no", PnvPhb4PecStack, stack_no, 0),
|
|
DEFINE_PROP_LINK("pec", PnvPhb4PecStack, pec, TYPE_PNV_PHB4_PEC,
|
|
PnvPhb4PecState *),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void pnv_pec_stk_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
device_class_set_props(dc, pnv_pec_stk_properties);
|
|
dc->realize = pnv_pec_stk_realize;
|
|
dc->user_creatable = false;
|
|
|
|
/* TODO: reset regs ? */
|
|
}
|
|
|
|
static const TypeInfo pnv_pec_stk_type_info = {
|
|
.name = TYPE_PNV_PHB4_PEC_STACK,
|
|
.parent = TYPE_DEVICE,
|
|
.instance_size = sizeof(PnvPhb4PecStack),
|
|
.instance_init = pnv_pec_stk_instance_init,
|
|
.class_init = pnv_pec_stk_class_init,
|
|
.interfaces = (InterfaceInfo[]) {
|
|
{ TYPE_PNV_XSCOM_INTERFACE },
|
|
{ }
|
|
}
|
|
};
|
|
|
|
static void pnv_pec_register_types(void)
|
|
{
|
|
type_register_static(&pnv_pec_type_info);
|
|
type_register_static(&pnv_pec_stk_type_info);
|
|
}
|
|
|
|
type_init(pnv_pec_register_types);
|