qemu/target-lm32 at 8d5192ee15bc519f83741f5e413ebba5d57a6abd - qemu

History

Stefan Weil 4b4a72e556 Fix conversions from pointer to tcg_target_long tcg_gen_exit_tb takes a parameter of type tcg_target_long, so the type casts of pointer to long should be replaced by type casts of pointer to tcg_target_long (suggested by Blue Swirl). These changes are needed for build environments where sizeof(long) != sizeof(void *), especially for w64. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>		2011-04-10 00:45:16 +02:00
..
cpu.h
exec.h
helper.c	lm32: translation routines	2011-03-07 13:42:36 +01:00
helper.h	lm32: translation code helper	2011-03-07 13:42:36 +01:00
machine.c	lm32: machine state loading/saving	2011-03-07 13:42:36 +01:00
op_helper.c	lm32: translation code helper	2011-03-07 13:42:36 +01:00
README	lm32: todo and documentation	2011-03-07 13:42:37 +01:00
TODO	lm32: todo and documentation	2011-03-07 13:42:37 +01:00
translate.c	Fix conversions from pointer to tcg_target_long	2011-04-10 00:45:16 +02:00

README

LatticeMico32 target
--------------------

General
-------
All opcodes including the JUART CSRs are supported.


JTAG UART
---------
JTAG UART is routed to a serial console device. For the current boards it
is the second one. Ie to enable it in the qemu virtual console window use
the following command line parameters:
  -serial vc -serial vc
This will make serial0 (the lm32_uart) and serial1 (the JTAG UART)
available as virtual consoles.


Programmatically terminate the emulator
----------------------------------------
Originally neither the LatticeMico32 nor its peripherals support a
mechanism to shut down the machine. Emulation aware programs can write to a
to a special register within the system control block to shut down the
virtual machine.  For more details see hw/lm32_sys.c. The lm32-evr is the
first BSP which instantiate this model. A (32 bit) write to 0xfff0000
causes a vm shutdown.


Special instructions
--------------------
The translation recognizes one special instruction to halt the cpu:
  and r0, r0, r0
On real hardware this instruction is a nop. It is not used by GCC and
should (hopefully) not be used within hand-crafted assembly.
Insert this instruction in your idle loop to reduce the cpu load on the
host.


Ignoring the MSB of the address bus
-----------------------------------
Some SoC ignores the MSB on the address bus. Thus creating a shadow memory
area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
0x80000000-0xffffffff is not cached and used to access IO devices. This
behaviour can be enabled with:
  cpu_lm32_set_phys_msb_ignore(env, 1);