c0c0461e3a
The la32 instructions listed in Table 2 at https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#overview-of-basic-integer-instructions Co-authored-by: Jiajie Chen <c@jia.je> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230822032724.1353391-9-gaosong@loongson.cn> Message-Id: <20230822071959.35620-3-philmd@linaro.org>
100 lines
2.9 KiB
PHP
100 lines
2.9 KiB
PHP
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2021 Loongson Technology Corporation Limited
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*/
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static void gen_sll_w(TCGv dest, TCGv src1, TCGv src2)
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{
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TCGv t0 = tcg_temp_new();
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tcg_gen_andi_tl(t0, src2, 0x1f);
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tcg_gen_shl_tl(dest, src1, t0);
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}
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static void gen_srl_w(TCGv dest, TCGv src1, TCGv src2)
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{
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TCGv t0 = tcg_temp_new();
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tcg_gen_andi_tl(t0, src2, 0x1f);
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tcg_gen_shr_tl(dest, src1, t0);
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}
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static void gen_sra_w(TCGv dest, TCGv src1, TCGv src2)
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{
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TCGv t0 = tcg_temp_new();
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tcg_gen_andi_tl(t0, src2, 0x1f);
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tcg_gen_sar_tl(dest, src1, t0);
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}
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static void gen_sll_d(TCGv dest, TCGv src1, TCGv src2)
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{
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TCGv t0 = tcg_temp_new();
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tcg_gen_andi_tl(t0, src2, 0x3f);
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tcg_gen_shl_tl(dest, src1, t0);
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}
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static void gen_srl_d(TCGv dest, TCGv src1, TCGv src2)
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{
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TCGv t0 = tcg_temp_new();
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tcg_gen_andi_tl(t0, src2, 0x3f);
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tcg_gen_shr_tl(dest, src1, t0);
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}
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static void gen_sra_d(TCGv dest, TCGv src1, TCGv src2)
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{
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TCGv t0 = tcg_temp_new();
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tcg_gen_andi_tl(t0, src2, 0x3f);
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tcg_gen_sar_tl(dest, src1, t0);
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}
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static void gen_rotr_w(TCGv dest, TCGv src1, TCGv src2)
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{
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TCGv_i32 t1 = tcg_temp_new_i32();
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TCGv_i32 t2 = tcg_temp_new_i32();
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TCGv t0 = tcg_temp_new();
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tcg_gen_andi_tl(t0, src2, 0x1f);
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tcg_gen_trunc_tl_i32(t1, src1);
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tcg_gen_trunc_tl_i32(t2, t0);
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tcg_gen_rotr_i32(t1, t1, t2);
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tcg_gen_ext_i32_tl(dest, t1);
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}
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static void gen_rotr_d(TCGv dest, TCGv src1, TCGv src2)
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{
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TCGv t0 = tcg_temp_new();
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tcg_gen_andi_tl(t0, src2, 0x3f);
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tcg_gen_rotr_tl(dest, src1, t0);
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}
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static bool trans_srai_w(DisasContext *ctx, arg_srai_w *a)
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{
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TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
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TCGv src1 = gpr_src(ctx, a->rj, EXT_ZERO);
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if (!avail_64(ctx)) {
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return false;
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}
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tcg_gen_sextract_tl(dest, src1, a->imm, 32 - a->imm);
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gen_set_gpr(a->rd, dest, EXT_NONE);
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return true;
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}
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TRANS(sll_w, ALL, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_sll_w)
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TRANS(srl_w, ALL, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_srl_w)
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TRANS(sra_w, ALL, gen_rrr, EXT_SIGN, EXT_NONE, EXT_SIGN, gen_sra_w)
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TRANS(sll_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sll_d)
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TRANS(srl_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_srl_d)
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TRANS(sra_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sra_d)
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TRANS(rotr_w, 64, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_rotr_w)
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TRANS(rotr_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rotr_d)
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TRANS(slli_w, ALL, gen_rri_c, EXT_NONE, EXT_SIGN, tcg_gen_shli_tl)
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TRANS(slli_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shli_tl)
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TRANS(srli_w, ALL, gen_rri_c, EXT_ZERO, EXT_SIGN, tcg_gen_shri_tl)
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TRANS(srli_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shri_tl)
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TRANS(srai_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_sari_tl)
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TRANS(rotri_w, 64, gen_rri_v, EXT_NONE, EXT_NONE, gen_rotr_w)
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TRANS(rotri_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_rotri_tl)
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