qemu/target/riscv/insn_trans
Bastian Koppelmann f330433b36
target/riscv: Fix manually parsed 16 bit insn
during the refactor to decodetree we removed the manual decoding that is
necessary for c.jal/c.addiw and removed the translation of c.flw/c.ld
and c.fsw/c.sd. This reintroduces the manual parsing and the
omited implementation.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Tested-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-03-17 22:21:32 -07:00
..
trans_privileged.inc.c target/riscv: Convert RV priv insns to decodetree 2019-03-13 10:34:06 +01:00
trans_rva.inc.c target/riscv: Convert RV64A insns to decodetree 2019-03-13 10:34:06 +01:00
trans_rvc.inc.c target/riscv: Fix manually parsed 16 bit insn 2019-03-17 22:21:32 -07:00
trans_rvd.inc.c target/riscv: Convert RV64D insns to decodetree 2019-03-13 10:34:06 +01:00
trans_rvf.inc.c target/riscv: Convert RV64F insns to decodetree 2019-03-13 10:34:06 +01:00
trans_rvi.inc.c target/riscv: Rename trans_arith to gen_arith 2019-03-13 10:40:50 +01:00
trans_rvm.inc.c target/riscv: Rename trans_arith to gen_arith 2019-03-13 10:40:50 +01:00