Peter Maydell 09d12c81ec hw/misc/grlib_ahb_apb_pnp: Support 8 and 16 bit accesses ... In real hardware, the APB and AHB PNP data tables can be accessed with byte and halfword reads as well as word reads. Our implementation currently only handles word reads. Add support for the 8 and 16 bit accesses. Note that we only need to handle aligned accesses -- unaligned accesses should continue to trap, as happens on hardware. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1132 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Frederic Konrad <fkonrad@amd.com> Message-Id: <20220802131925.3380923-1-peter.maydell@linaro.org> Tested-by: Tomasz Martyniak <gitlab.com/tom4r> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>		2022-08-08 23:43:11 +02:00
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macio
a9scu.c
allwinner-cpucfg.c
allwinner-h3-ccu.c
allwinner-h3-dramc.c
allwinner-h3-sysctrl.c
allwinner-sid.c
applesmc.c
arm11scu.c
arm_integrator_debug.c
arm_l2x0.c
arm_sysctl.c
armsse-cpu-pwrctrl.c
armsse-cpuid.c
armsse-mhu.c
armv7m_ras.c
aspeed_hace.c
aspeed_i3c.c
aspeed_lpc.c
aspeed_peci.c
aspeed_sbc.c	aspeed: sbc: Allow per-machine settings	2022-07-14 16:24:38 +02:00
aspeed_scu.c
aspeed_sdmc.c
aspeed_xdma.c
auxbus.c
avr_power.c
bcm2835_cprman.c
bcm2835_mbox.c
bcm2835_mphi.c
bcm2835_powermgt.c
bcm2835_property.c
bcm2835_rng.c
bcm2835_thermal.c
cbus.c
debugexit.c
eccmemctl.c
edu.c
empty_slot.c
exynos4210_clk.c
exynos4210_pmu.c
exynos4210_rng.c
grlib_ahb_apb_pnp.c	hw/misc/grlib_ahb_apb_pnp: Support 8 and 16 bit accesses	2022-08-08 23:43:11 +02:00
imx6_ccm.c
imx6_src.c
imx6ul_ccm.c
imx7_ccm.c
imx7_gpr.c
imx7_snvs.c
imx25_ccm.c
imx31_ccm.c
imx_ccm.c
imx_rngc.c
iotkit-secctl.c	misc: fix commonly doubled up words	2022-08-01 11:58:02 +02:00
iotkit-sysctl.c	misc: fix commonly doubled up words	2022-08-01 11:58:02 +02:00
iotkit-sysinfo.c
ivshmem.c
Kconfig
lasi.c
led.c
mac_via.c	trivial: Fix duplicated words	2022-08-01 11:58:02 +02:00
mchp_pfsoc_dmc.c
mchp_pfsoc_ioscb.c
mchp_pfsoc_sysreg.c
meson.build
mips_cmgcr.c
mips_cpc.c
mips_itu.c
mos6522.c
mps2-fpgaio.c
mps2-scc.c
msf2-sysreg.c
mst_fpga.c
npcm7xx_clk.c
npcm7xx_gcr.c
npcm7xx_mft.c
npcm7xx_pwm.c
npcm7xx_rng.c
nrf51_rng.c
omap_clk.c
omap_gpmc.c
omap_l4.c
omap_sdrc.c
omap_tap.c
pc-testdev.c
pca9552.c
pci-testdev.c
pvpanic-isa.c
pvpanic-pci.c
pvpanic.c
sbsa_ec.c
sga.c
sifive_e_prci.c
sifive_test.c
sifive_u_otp.c	block: Change blk_{pread,pwrite}() param order	2022-07-12 12:14:56 +02:00
sifive_u_prci.c
slavio_misc.c
stm32f2xx_syscfg.c
stm32f4xx_exti.c
stm32f4xx_syscfg.c
trace-events	hw/misc/grlib_ahb_apb_pnp: Support 8 and 16 bit accesses	2022-08-08 23:43:11 +02:00
trace.h
tz-mpc.c
tz-msc.c
tz-ppc.c
unimp.c
virt_ctrl.c
vmcoreinfo.c
xlnx-versal-crl.c
xlnx-versal-pmc-iou-slcr.c
xlnx-versal-xramc.c
xlnx-zynqmp-apu-ctrl.c
xlnx-zynqmp-crf.c
zynq_slcr.c