Xi Wang ff9f31d9a0 target/riscv: fix counter-enable checks in ctr() ... Access to a counter in U-mode is permitted only if the corresponding bit is set in both mcounteren and scounteren. The current code ignores mcounteren and checks scounteren only for U-mode access. Signed-off-by: Xi Wang <xi.wang@gmail.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2019-02-11 15:56:22 -08:00
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cpu_bits.h
cpu_helper.c
cpu_user.h
cpu.c
cpu.h
csr.c	target/riscv: fix counter-enable checks in ctr()	2019-02-11 15:56:22 -08:00
fpu_helper.c
gdbstub.c
helper.h
instmap.h
Makefile.objs
op_helper.c
pmp.c
pmp.h
translate.c