Jiaxun Yang 03afdc28b3 target/mips: Implement Loongson CSR instructions ... Loongson introduced CSR instructions since 3A4000, which looks similar to IOCSR and CPUCFG instructions we seen in LoongArch. Unfortunately we don't have much document about those instructions, bit fields of CPUCFG instructions and IOCSR registers can be found at 3A4000's user manual, while instruction encodings can be found at arch/mips/include/asm/mach-loongson64/loongson_regs.h from Linux Kernel. Our predefined CPUCFG bits are differ from actual 3A4000, since we can't emulate all CPUCFG features present in 3A4000 for now, we just enable bits for what we have in TCG. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20230521214832.20145-2-jiaxun.yang@flygoat.com> [JY: Fixed typo in ase_lcsr_available(), retrict GEN_FALSE_TRANS] [PMD: Fix meson's mips_softmmu_ss -> mips_system_ss, restrict AddressSpace/MemoryRegion to SysEmu] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>		2023-07-10 23:33:37 +02:00
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cp0_helper.c	target/mips: Fix WatchHi.M handling	2022-06-11 11:34:12 +02:00
lcsr_helper.c	target/mips: Implement Loongson CSR instructions	2023-07-10 23:33:37 +02:00
meson.build	target/mips: Implement Loongson CSR instructions	2023-07-10 23:33:37 +02:00
mips-semi.c	gdbstub: move syscall handling to new file	2023-03-07 20:44:08 +00:00
special_helper.c	target/mips: Replace tb_pc() with tb->pc	2023-03-01 07:33:17 -10:00
tlb_helper.c	bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx	2023-01-18 11:14:34 +01:00