KONRAD Frederic 89fca22f21 booke206: fix MAS update on tlb miss ... When a tlb instruction miss happen, rw is set to 0 at the bottom of cpu_ppc_handle_mmu_fault which cause the MAS update function to miss the SAS and TS bit in MAS6, MAS1 in booke206_update_mas_tlb_miss. Just calling booke206_update_mas_tlb_miss with rw = 2 solve the issue. Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>		2017-08-09 11:46:44 +10:00
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alpha	tcg: Pass generic CPUState to gen_intermediate_code()	2017-07-19 14:45:16 -07:00
arm	trace-events: fix code style: print 0x before hex numbers	2017-08-01 12:13:07 +01:00
cris	tcg: Pass generic CPUState to gen_intermediate_code()	2017-07-19 14:45:16 -07:00
hppa	tcg: Pass generic CPUState to gen_intermediate_code()	2017-07-19 14:45:16 -07:00
i386	target/i386: set rip_offset for some SSE4.1 instructions	2017-08-08 10:40:20 +02:00
lm32	tcg: Pass generic CPUState to gen_intermediate_code()	2017-07-19 14:45:16 -07:00
m68k	m68k/translate: fix incorrect copy/paste	2017-07-31 13:06:39 +03:00
microblaze	tcg: Pass generic CPUState to gen_intermediate_code()	2017-07-19 14:45:16 -07:00
mips	target/mips: Fix RDHWR CC with icount	2017-08-02 22:18:13 +01:00
moxie	tcg: Pass generic CPUState to gen_intermediate_code()	2017-07-19 14:45:16 -07:00
nios2	tcg: Pass generic CPUState to gen_intermediate_code()	2017-07-19 14:45:16 -07:00
openrisc	tcg: Pass generic CPUState to gen_intermediate_code()	2017-07-19 14:45:16 -07:00
ppc	booke206: fix MAS update on tlb miss	2017-08-09 11:46:44 +10:00
s390x	target/s390x: Fix CSST for 16-byte store	2017-08-03 10:58:50 -07:00
sh4	tcg: Pass generic CPUState to gen_intermediate_code()	2017-07-19 14:45:16 -07:00
sparc	trace-events: fix code style: print 0x before hex numbers	2017-08-01 12:13:07 +01:00
tilegx	tcg: Pass generic CPUState to gen_intermediate_code()	2017-07-19 14:45:16 -07:00
tricore	qemu-system-tricore: segfault when entering "x 0" on the monitor	2017-07-31 13:06:38 +03:00
unicore32	tcg: Pass generic CPUState to gen_intermediate_code()	2017-07-19 14:45:16 -07:00
xtensa	tcg: Pass generic CPUState to gen_intermediate_code()	2017-07-19 14:45:16 -07:00