29bbccc278
Let's report IO-coherent access is supported for translation
table walks, descriptor fetches and queues by setting the COHACC
override flag. Without that, we observe wrong command opcodes.
The DT description also advertises the dma coherency.
Fixes a703b4f6c1 ("hw/arm/virt-acpi-build: Add smmuv3 node in IORT table")
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reported-by: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>
Tested-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-id: 20190107101041.765-1-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
656 lines
20 KiB
C
656 lines
20 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef QEMU_ACPI_DEFS_H
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#define QEMU_ACPI_DEFS_H
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enum {
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ACPI_FADT_F_WBINVD,
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ACPI_FADT_F_WBINVD_FLUSH,
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ACPI_FADT_F_PROC_C1,
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ACPI_FADT_F_P_LVL2_UP,
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ACPI_FADT_F_PWR_BUTTON,
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ACPI_FADT_F_SLP_BUTTON,
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ACPI_FADT_F_FIX_RTC,
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ACPI_FADT_F_RTC_S4,
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ACPI_FADT_F_TMR_VAL_EXT,
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ACPI_FADT_F_DCK_CAP,
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ACPI_FADT_F_RESET_REG_SUP,
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ACPI_FADT_F_SEALED_CASE,
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ACPI_FADT_F_HEADLESS,
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ACPI_FADT_F_CPU_SW_SLP,
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ACPI_FADT_F_PCI_EXP_WAK,
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ACPI_FADT_F_USE_PLATFORM_CLOCK,
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ACPI_FADT_F_S4_RTC_STS_VALID,
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ACPI_FADT_F_REMOTE_POWER_ON_CAPABLE,
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ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL,
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ACPI_FADT_F_FORCE_APIC_PHYSICAL_DESTINATION_MODE,
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ACPI_FADT_F_HW_REDUCED_ACPI,
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ACPI_FADT_F_LOW_POWER_S0_IDLE_CAPABLE,
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};
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typedef struct AcpiRsdpData {
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uint8_t oem_id[6] QEMU_NONSTRING; /* OEM identification */
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uint8_t revision; /* Must be 0 for 1.0, 2 for 2.0 */
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unsigned *rsdt_tbl_offset;
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unsigned *xsdt_tbl_offset;
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} AcpiRsdpData;
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/* Table structure from Linux kernel (the ACPI tables are under the
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BSD license) */
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#define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
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uint32_t signature; /* ACPI signature (4 ASCII characters) */ \
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uint32_t length; /* Length of table, in bytes, including header */ \
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uint8_t revision; /* ACPI Specification minor version # */ \
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uint8_t checksum; /* To make sum of entire table == 0 */ \
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uint8_t oem_id[6] \
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QEMU_NONSTRING; /* OEM identification */ \
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uint8_t oem_table_id[8] \
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QEMU_NONSTRING; /* OEM table identification */ \
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uint32_t oem_revision; /* OEM revision number */ \
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uint8_t asl_compiler_id[4] \
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QEMU_NONSTRING; /* ASL compiler vendor ID */ \
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uint32_t asl_compiler_revision; /* ASL compiler revision number */
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/* ACPI common table header */
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struct AcpiTableHeader {
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ACPI_TABLE_HEADER_DEF
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} QEMU_PACKED;
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typedef struct AcpiTableHeader AcpiTableHeader;
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struct AcpiGenericAddress {
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uint8_t space_id; /* Address space where struct or register exists */
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uint8_t bit_width; /* Size in bits of given register */
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uint8_t bit_offset; /* Bit offset within the register */
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uint8_t access_width; /* ACPI 3.0: Minimum Access size (ACPI 3.0),
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ACPI 2.0: Reserved, Table 5-1 */
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uint64_t address; /* 64-bit address of struct or register */
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} QEMU_PACKED;
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typedef struct AcpiFadtData {
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struct AcpiGenericAddress pm1a_cnt; /* PM1a_CNT_BLK */
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struct AcpiGenericAddress pm1a_evt; /* PM1a_EVT_BLK */
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struct AcpiGenericAddress pm_tmr; /* PM_TMR_BLK */
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struct AcpiGenericAddress gpe0_blk; /* GPE0_BLK */
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struct AcpiGenericAddress reset_reg; /* RESET_REG */
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uint8_t reset_val; /* RESET_VALUE */
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uint8_t rev; /* Revision */
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uint32_t flags; /* Flags */
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uint32_t smi_cmd; /* SMI_CMD */
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uint16_t sci_int; /* SCI_INT */
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uint8_t int_model; /* INT_MODEL */
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uint8_t acpi_enable_cmd; /* ACPI_ENABLE */
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uint8_t acpi_disable_cmd; /* ACPI_DISABLE */
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uint8_t rtc_century; /* CENTURY */
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uint16_t plvl2_lat; /* P_LVL2_LAT */
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uint16_t plvl3_lat; /* P_LVL3_LAT */
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uint16_t arm_boot_arch; /* ARM_BOOT_ARCH */
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uint8_t minor_ver; /* FADT Minor Version */
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/*
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* respective tables offsets within ACPI_BUILD_TABLE_FILE,
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* NULL if table doesn't exist (in that case field's value
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* won't be patched by linker and will be kept set to 0)
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*/
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unsigned *facs_tbl_offset; /* FACS offset in */
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unsigned *dsdt_tbl_offset;
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unsigned *xdsdt_tbl_offset;
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} AcpiFadtData;
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#define ACPI_FADT_ARM_PSCI_COMPLIANT (1 << 0)
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#define ACPI_FADT_ARM_PSCI_USE_HVC (1 << 1)
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/*
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* Serial Port Console Redirection Table (SPCR), Rev. 1.02
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*
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* For .interface_type see Debug Port Table 2 (DBG2) serial port
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* subtypes in Table 3, Rev. May 22, 2012
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*/
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struct AcpiSerialPortConsoleRedirection {
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ACPI_TABLE_HEADER_DEF
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uint8_t interface_type;
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uint8_t reserved1[3];
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struct AcpiGenericAddress base_address;
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uint8_t interrupt_types;
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uint8_t irq;
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uint32_t gsi;
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uint8_t baud;
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uint8_t parity;
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uint8_t stopbits;
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uint8_t flowctrl;
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uint8_t term_type;
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uint8_t reserved2;
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uint16_t pci_device_id;
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uint16_t pci_vendor_id;
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uint8_t pci_bus;
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uint8_t pci_slot;
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uint8_t pci_func;
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uint32_t pci_flags;
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uint8_t pci_seg;
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uint32_t reserved3;
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} QEMU_PACKED;
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typedef struct AcpiSerialPortConsoleRedirection
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AcpiSerialPortConsoleRedirection;
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/*
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* ACPI 1.0 Root System Description Table (RSDT)
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*/
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struct AcpiRsdtDescriptorRev1 {
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ACPI_TABLE_HEADER_DEF /* ACPI common table header */
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uint32_t table_offset_entry[0]; /* Array of pointers to other */
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/* ACPI tables */
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} QEMU_PACKED;
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typedef struct AcpiRsdtDescriptorRev1 AcpiRsdtDescriptorRev1;
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/*
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* ACPI 2.0 eXtended System Description Table (XSDT)
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*/
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struct AcpiXsdtDescriptorRev2 {
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ACPI_TABLE_HEADER_DEF /* ACPI common table header */
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uint64_t table_offset_entry[0]; /* Array of pointers to other */
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/* ACPI tables */
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} QEMU_PACKED;
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typedef struct AcpiXsdtDescriptorRev2 AcpiXsdtDescriptorRev2;
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/*
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* ACPI 1.0 Firmware ACPI Control Structure (FACS)
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*/
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struct AcpiFacsDescriptorRev1 {
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uint32_t signature; /* ACPI Signature */
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uint32_t length; /* Length of structure, in bytes */
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uint32_t hardware_signature; /* Hardware configuration signature */
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uint32_t firmware_waking_vector; /* ACPI OS waking vector */
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uint32_t global_lock; /* Global Lock */
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uint32_t flags;
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uint8_t resverved3 [40]; /* Reserved - must be zero */
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} QEMU_PACKED;
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typedef struct AcpiFacsDescriptorRev1 AcpiFacsDescriptorRev1;
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/*
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* Differentiated System Description Table (DSDT)
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*/
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/*
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* MADT values and structures
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*/
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/* Values for MADT PCATCompat */
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#define ACPI_DUAL_PIC 0
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#define ACPI_MULTIPLE_APIC 1
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/* Master MADT */
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struct AcpiMultipleApicTable {
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ACPI_TABLE_HEADER_DEF /* ACPI common table header */
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uint32_t local_apic_address; /* Physical address of local APIC */
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uint32_t flags;
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} QEMU_PACKED;
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typedef struct AcpiMultipleApicTable AcpiMultipleApicTable;
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/* Values for Type in APIC sub-headers */
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#define ACPI_APIC_PROCESSOR 0
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#define ACPI_APIC_IO 1
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#define ACPI_APIC_XRUPT_OVERRIDE 2
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#define ACPI_APIC_NMI 3
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#define ACPI_APIC_LOCAL_NMI 4
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#define ACPI_APIC_ADDRESS_OVERRIDE 5
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#define ACPI_APIC_IO_SAPIC 6
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#define ACPI_APIC_LOCAL_SAPIC 7
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#define ACPI_APIC_XRUPT_SOURCE 8
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#define ACPI_APIC_LOCAL_X2APIC 9
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#define ACPI_APIC_LOCAL_X2APIC_NMI 10
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#define ACPI_APIC_GENERIC_CPU_INTERFACE 11
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#define ACPI_APIC_GENERIC_DISTRIBUTOR 12
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#define ACPI_APIC_GENERIC_MSI_FRAME 13
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#define ACPI_APIC_GENERIC_REDISTRIBUTOR 14
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#define ACPI_APIC_GENERIC_TRANSLATOR 15
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#define ACPI_APIC_RESERVED 16 /* 16 and greater are reserved */
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/*
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* MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
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*/
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#define ACPI_SUB_HEADER_DEF /* Common ACPI sub-structure header */\
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uint8_t type; \
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uint8_t length;
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/* Sub-structures for MADT */
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struct AcpiMadtProcessorApic {
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ACPI_SUB_HEADER_DEF
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uint8_t processor_id; /* ACPI processor id */
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uint8_t local_apic_id; /* Processor's local APIC id */
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uint32_t flags;
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} QEMU_PACKED;
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typedef struct AcpiMadtProcessorApic AcpiMadtProcessorApic;
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struct AcpiMadtIoApic {
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ACPI_SUB_HEADER_DEF
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uint8_t io_apic_id; /* I/O APIC ID */
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uint8_t reserved; /* Reserved - must be zero */
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uint32_t address; /* APIC physical address */
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uint32_t interrupt; /* Global system interrupt where INTI
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* lines start */
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} QEMU_PACKED;
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typedef struct AcpiMadtIoApic AcpiMadtIoApic;
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struct AcpiMadtIntsrcovr {
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ACPI_SUB_HEADER_DEF
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uint8_t bus;
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uint8_t source;
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uint32_t gsi;
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uint16_t flags;
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} QEMU_PACKED;
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typedef struct AcpiMadtIntsrcovr AcpiMadtIntsrcovr;
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struct AcpiMadtLocalNmi {
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ACPI_SUB_HEADER_DEF
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uint8_t processor_id; /* ACPI processor id */
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uint16_t flags; /* MPS INTI flags */
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uint8_t lint; /* Local APIC LINT# */
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} QEMU_PACKED;
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typedef struct AcpiMadtLocalNmi AcpiMadtLocalNmi;
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struct AcpiMadtProcessorX2Apic {
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ACPI_SUB_HEADER_DEF
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uint16_t reserved;
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uint32_t x2apic_id; /* Processor's local x2APIC ID */
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uint32_t flags;
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uint32_t uid; /* Processor object _UID */
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} QEMU_PACKED;
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typedef struct AcpiMadtProcessorX2Apic AcpiMadtProcessorX2Apic;
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struct AcpiMadtLocalX2ApicNmi {
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ACPI_SUB_HEADER_DEF
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uint16_t flags; /* MPS INTI flags */
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uint32_t uid; /* Processor object _UID */
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uint8_t lint; /* Local APIC LINT# */
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uint8_t reserved[3]; /* Local APIC LINT# */
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} QEMU_PACKED;
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typedef struct AcpiMadtLocalX2ApicNmi AcpiMadtLocalX2ApicNmi;
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struct AcpiMadtGenericCpuInterface {
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ACPI_SUB_HEADER_DEF
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uint16_t reserved;
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uint32_t cpu_interface_number;
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uint32_t uid;
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uint32_t flags;
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uint32_t parking_version;
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uint32_t performance_interrupt;
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uint64_t parked_address;
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uint64_t base_address;
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uint64_t gicv_base_address;
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uint64_t gich_base_address;
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uint32_t vgic_interrupt;
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uint64_t gicr_base_address;
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uint64_t arm_mpidr;
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} QEMU_PACKED;
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typedef struct AcpiMadtGenericCpuInterface AcpiMadtGenericCpuInterface;
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/* GICC CPU Interface Flags */
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#define ACPI_MADT_GICC_ENABLED 1
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struct AcpiMadtGenericDistributor {
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ACPI_SUB_HEADER_DEF
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uint16_t reserved;
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uint32_t gic_id;
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uint64_t base_address;
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uint32_t global_irq_base;
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/* ACPI 5.1 Errata 1228 Present GIC version in MADT table */
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uint8_t version;
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uint8_t reserved2[3];
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} QEMU_PACKED;
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typedef struct AcpiMadtGenericDistributor AcpiMadtGenericDistributor;
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struct AcpiMadtGenericMsiFrame {
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ACPI_SUB_HEADER_DEF
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uint16_t reserved;
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uint32_t gic_msi_frame_id;
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uint64_t base_address;
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uint32_t flags;
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uint16_t spi_count;
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uint16_t spi_base;
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} QEMU_PACKED;
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typedef struct AcpiMadtGenericMsiFrame AcpiMadtGenericMsiFrame;
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struct AcpiMadtGenericRedistributor {
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ACPI_SUB_HEADER_DEF
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uint16_t reserved;
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uint64_t base_address;
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uint32_t range_length;
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} QEMU_PACKED;
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typedef struct AcpiMadtGenericRedistributor AcpiMadtGenericRedistributor;
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struct AcpiMadtGenericTranslator {
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ACPI_SUB_HEADER_DEF
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uint16_t reserved;
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uint32_t translation_id;
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uint64_t base_address;
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uint32_t reserved2;
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} QEMU_PACKED;
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typedef struct AcpiMadtGenericTranslator AcpiMadtGenericTranslator;
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/*
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* Generic Timer Description Table (GTDT)
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*/
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#define ACPI_GTDT_INTERRUPT_MODE_LEVEL (0 << 0)
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#define ACPI_GTDT_INTERRUPT_MODE_EDGE (1 << 0)
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#define ACPI_GTDT_CAP_ALWAYS_ON (1 << 2)
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struct AcpiGenericTimerTable {
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ACPI_TABLE_HEADER_DEF
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uint64_t counter_block_addresss;
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uint32_t reserved;
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uint32_t secure_el1_interrupt;
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uint32_t secure_el1_flags;
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uint32_t non_secure_el1_interrupt;
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uint32_t non_secure_el1_flags;
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uint32_t virtual_timer_interrupt;
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uint32_t virtual_timer_flags;
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uint32_t non_secure_el2_interrupt;
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uint32_t non_secure_el2_flags;
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uint64_t counter_read_block_address;
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uint32_t platform_timer_count;
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uint32_t platform_timer_offset;
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} QEMU_PACKED;
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typedef struct AcpiGenericTimerTable AcpiGenericTimerTable;
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/*
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* HPET Description Table
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*/
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struct Acpi20Hpet {
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ACPI_TABLE_HEADER_DEF /* ACPI common table header */
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uint32_t timer_block_id;
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struct AcpiGenericAddress addr;
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uint8_t hpet_number;
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uint16_t min_tick;
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uint8_t page_protect;
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} QEMU_PACKED;
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typedef struct Acpi20Hpet Acpi20Hpet;
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/*
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* SRAT (NUMA topology description) table
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*/
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struct AcpiSystemResourceAffinityTable {
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ACPI_TABLE_HEADER_DEF
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uint32_t reserved1;
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uint32_t reserved2[2];
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} QEMU_PACKED;
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typedef struct AcpiSystemResourceAffinityTable AcpiSystemResourceAffinityTable;
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#define ACPI_SRAT_PROCESSOR_APIC 0
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#define ACPI_SRAT_MEMORY 1
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#define ACPI_SRAT_PROCESSOR_x2APIC 2
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#define ACPI_SRAT_PROCESSOR_GICC 3
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struct AcpiSratProcessorAffinity {
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ACPI_SUB_HEADER_DEF
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uint8_t proximity_lo;
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uint8_t local_apic_id;
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uint32_t flags;
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uint8_t local_sapic_eid;
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uint8_t proximity_hi[3];
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uint32_t reserved;
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} QEMU_PACKED;
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typedef struct AcpiSratProcessorAffinity AcpiSratProcessorAffinity;
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struct AcpiSratProcessorX2ApicAffinity {
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ACPI_SUB_HEADER_DEF
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uint16_t reserved;
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uint32_t proximity_domain;
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uint32_t x2apic_id;
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uint32_t flags;
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uint32_t clk_domain;
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uint32_t reserved2;
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} QEMU_PACKED;
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typedef struct AcpiSratProcessorX2ApicAffinity AcpiSratProcessorX2ApicAffinity;
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struct AcpiSratMemoryAffinity {
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ACPI_SUB_HEADER_DEF
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uint32_t proximity;
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uint16_t reserved1;
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uint64_t base_addr;
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uint64_t range_length;
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uint32_t reserved2;
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uint32_t flags;
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uint32_t reserved3[2];
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} QEMU_PACKED;
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typedef struct AcpiSratMemoryAffinity AcpiSratMemoryAffinity;
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struct AcpiSratProcessorGiccAffinity {
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ACPI_SUB_HEADER_DEF
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uint32_t proximity;
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uint32_t acpi_processor_uid;
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uint32_t flags;
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uint32_t clock_domain;
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} QEMU_PACKED;
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typedef struct AcpiSratProcessorGiccAffinity AcpiSratProcessorGiccAffinity;
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/* PCI fw r3.0 MCFG table. */
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/* Subtable */
|
|
struct AcpiMcfgAllocation {
|
|
uint64_t address; /* Base address, processor-relative */
|
|
uint16_t pci_segment; /* PCI segment group number */
|
|
uint8_t start_bus_number; /* Starting PCI Bus number */
|
|
uint8_t end_bus_number; /* Final PCI Bus number */
|
|
uint32_t reserved;
|
|
} QEMU_PACKED;
|
|
typedef struct AcpiMcfgAllocation AcpiMcfgAllocation;
|
|
|
|
struct AcpiTableMcfg {
|
|
ACPI_TABLE_HEADER_DEF;
|
|
uint8_t reserved[8];
|
|
AcpiMcfgAllocation allocation[0];
|
|
} QEMU_PACKED;
|
|
typedef struct AcpiTableMcfg AcpiTableMcfg;
|
|
|
|
/*
|
|
* TCPA Description Table
|
|
*
|
|
* Following Level 00, Rev 00.37 of specs:
|
|
* http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification
|
|
*/
|
|
struct Acpi20Tcpa {
|
|
ACPI_TABLE_HEADER_DEF /* ACPI common table header */
|
|
uint16_t platform_class;
|
|
uint32_t log_area_minimum_length;
|
|
uint64_t log_area_start_address;
|
|
} QEMU_PACKED;
|
|
typedef struct Acpi20Tcpa Acpi20Tcpa;
|
|
|
|
/*
|
|
* TPM2
|
|
*
|
|
* Following Version 1.2, Revision 8 of specs:
|
|
* https://trustedcomputinggroup.org/tcg-acpi-specification/
|
|
*/
|
|
struct Acpi20TPM2 {
|
|
ACPI_TABLE_HEADER_DEF
|
|
uint16_t platform_class;
|
|
uint16_t reserved;
|
|
uint64_t control_area_address;
|
|
uint32_t start_method;
|
|
uint8_t start_method_params[12];
|
|
uint32_t log_area_minimum_length;
|
|
uint64_t log_area_start_address;
|
|
} QEMU_PACKED;
|
|
typedef struct Acpi20TPM2 Acpi20TPM2;
|
|
|
|
/* DMAR - DMA Remapping table r2.2 */
|
|
struct AcpiTableDmar {
|
|
ACPI_TABLE_HEADER_DEF
|
|
uint8_t host_address_width; /* Maximum DMA physical addressability */
|
|
uint8_t flags;
|
|
uint8_t reserved[10];
|
|
} QEMU_PACKED;
|
|
typedef struct AcpiTableDmar AcpiTableDmar;
|
|
|
|
/* Masks for Flags field above */
|
|
#define ACPI_DMAR_INTR_REMAP 1
|
|
#define ACPI_DMAR_X2APIC_OPT_OUT (1 << 1)
|
|
|
|
/* Values for sub-structure type for DMAR */
|
|
enum {
|
|
ACPI_DMAR_TYPE_HARDWARE_UNIT = 0, /* DRHD */
|
|
ACPI_DMAR_TYPE_RESERVED_MEMORY = 1, /* RMRR */
|
|
ACPI_DMAR_TYPE_ATSR = 2, /* ATSR */
|
|
ACPI_DMAR_TYPE_HARDWARE_AFFINITY = 3, /* RHSR */
|
|
ACPI_DMAR_TYPE_ANDD = 4, /* ANDD */
|
|
ACPI_DMAR_TYPE_RESERVED = 5 /* Reserved for furture use */
|
|
};
|
|
|
|
/*
|
|
* Sub-structures for DMAR
|
|
*/
|
|
|
|
/* Device scope structure for DRHD. */
|
|
struct AcpiDmarDeviceScope {
|
|
uint8_t entry_type;
|
|
uint8_t length;
|
|
uint16_t reserved;
|
|
uint8_t enumeration_id;
|
|
uint8_t bus;
|
|
struct {
|
|
uint8_t device;
|
|
uint8_t function;
|
|
} path[0];
|
|
} QEMU_PACKED;
|
|
typedef struct AcpiDmarDeviceScope AcpiDmarDeviceScope;
|
|
|
|
/* Type 0: Hardware Unit Definition */
|
|
struct AcpiDmarHardwareUnit {
|
|
uint16_t type;
|
|
uint16_t length;
|
|
uint8_t flags;
|
|
uint8_t reserved;
|
|
uint16_t pci_segment; /* The PCI Segment associated with this unit */
|
|
uint64_t address; /* Base address of remapping hardware register-set */
|
|
AcpiDmarDeviceScope scope[0];
|
|
} QEMU_PACKED;
|
|
typedef struct AcpiDmarHardwareUnit AcpiDmarHardwareUnit;
|
|
|
|
/* Type 2: Root Port ATS Capability Reporting Structure */
|
|
struct AcpiDmarRootPortATS {
|
|
uint16_t type;
|
|
uint16_t length;
|
|
uint8_t flags;
|
|
uint8_t reserved;
|
|
uint16_t pci_segment;
|
|
AcpiDmarDeviceScope scope[0];
|
|
} QEMU_PACKED;
|
|
typedef struct AcpiDmarRootPortATS AcpiDmarRootPortATS;
|
|
|
|
/* Masks for Flags field above */
|
|
#define ACPI_DMAR_INCLUDE_PCI_ALL 1
|
|
#define ACPI_DMAR_ATSR_ALL_PORTS 1
|
|
|
|
/*
|
|
* Input Output Remapping Table (IORT)
|
|
* Conforms to "IO Remapping Table System Software on ARM Platforms",
|
|
* Document number: ARM DEN 0049B, October 2015
|
|
*/
|
|
|
|
struct AcpiIortTable {
|
|
ACPI_TABLE_HEADER_DEF /* ACPI common table header */
|
|
uint32_t node_count;
|
|
uint32_t node_offset;
|
|
uint32_t reserved;
|
|
} QEMU_PACKED;
|
|
typedef struct AcpiIortTable AcpiIortTable;
|
|
|
|
/*
|
|
* IORT node types
|
|
*/
|
|
|
|
#define ACPI_IORT_NODE_HEADER_DEF /* Node format common fields */ \
|
|
uint8_t type; \
|
|
uint16_t length; \
|
|
uint8_t revision; \
|
|
uint32_t reserved; \
|
|
uint32_t mapping_count; \
|
|
uint32_t mapping_offset;
|
|
|
|
/* Values for node Type above */
|
|
enum {
|
|
ACPI_IORT_NODE_ITS_GROUP = 0x00,
|
|
ACPI_IORT_NODE_NAMED_COMPONENT = 0x01,
|
|
ACPI_IORT_NODE_PCI_ROOT_COMPLEX = 0x02,
|
|
ACPI_IORT_NODE_SMMU = 0x03,
|
|
ACPI_IORT_NODE_SMMU_V3 = 0x04
|
|
};
|
|
|
|
struct AcpiIortIdMapping {
|
|
uint32_t input_base;
|
|
uint32_t id_count;
|
|
uint32_t output_base;
|
|
uint32_t output_reference;
|
|
uint32_t flags;
|
|
} QEMU_PACKED;
|
|
typedef struct AcpiIortIdMapping AcpiIortIdMapping;
|
|
|
|
struct AcpiIortMemoryAccess {
|
|
uint32_t cache_coherency;
|
|
uint8_t hints;
|
|
uint16_t reserved;
|
|
uint8_t memory_flags;
|
|
} QEMU_PACKED;
|
|
typedef struct AcpiIortMemoryAccess AcpiIortMemoryAccess;
|
|
|
|
struct AcpiIortItsGroup {
|
|
ACPI_IORT_NODE_HEADER_DEF
|
|
uint32_t its_count;
|
|
uint32_t identifiers[0];
|
|
} QEMU_PACKED;
|
|
typedef struct AcpiIortItsGroup AcpiIortItsGroup;
|
|
|
|
#define ACPI_IORT_SMMU_V3_COHACC_OVERRIDE 1
|
|
|
|
struct AcpiIortSmmu3 {
|
|
ACPI_IORT_NODE_HEADER_DEF
|
|
uint64_t base_address;
|
|
uint32_t flags;
|
|
uint32_t reserved2;
|
|
uint64_t vatos_address;
|
|
uint32_t model;
|
|
uint32_t event_gsiv;
|
|
uint32_t pri_gsiv;
|
|
uint32_t gerr_gsiv;
|
|
uint32_t sync_gsiv;
|
|
AcpiIortIdMapping id_mapping_array[0];
|
|
} QEMU_PACKED;
|
|
typedef struct AcpiIortSmmu3 AcpiIortSmmu3;
|
|
|
|
struct AcpiIortRC {
|
|
ACPI_IORT_NODE_HEADER_DEF
|
|
AcpiIortMemoryAccess memory_properties;
|
|
uint32_t ats_attribute;
|
|
uint32_t pci_segment_number;
|
|
AcpiIortIdMapping id_mapping_array[0];
|
|
} QEMU_PACKED;
|
|
typedef struct AcpiIortRC AcpiIortRC;
|
|
|
|
#endif
|