Richard Henderson 89c883091f target/riscv: Use DisasExtend in shift operations ... These operations are greatly simplified by ctx->w, which allows us to fold gen_shiftw into gen_shift. Split gen_shifti into gen_shift_imm_{fn,tl} like we do for gen_arith_imm_{fn,tl}. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-13-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-09-01 11:59:12 +10:00
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trans_privileged.c.inc	riscv: Add semihosting support	2021-01-18 10:05:06 +00:00
trans_rva.c.inc	target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr	2021-09-01 11:59:12 +10:00
trans_rvb.c.inc	target/riscv: Use DisasExtend in shift operations	2021-09-01 11:59:12 +10:00
trans_rvd.c.inc	target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr	2021-09-01 11:59:12 +10:00
trans_rvf.c.inc	target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr	2021-09-01 11:59:12 +10:00
trans_rvh.c.inc	target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr	2021-09-01 11:59:12 +10:00
trans_rvi.c.inc	target/riscv: Use DisasExtend in shift operations	2021-09-01 11:59:12 +10:00
trans_rvm.c.inc	target/riscv: Move gen_* helpers for RVM	2021-09-01 11:59:12 +10:00
trans_rvv.c.inc	target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr	2021-09-01 11:59:12 +10:00