qemu/target-arm
Peter Maydell 891a2fe720 target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAE
Under LPAE, the cp15 registers PAR, TTBR0 and TTBR1 are extended
to 64 bits, with a 64 bit (MRRC/MCRR) access path to read the
full width of the register. Add the state fields for the top
half and the 64 bit access path. Actual use of the top half of
the register will come with the addition of the long-descriptor
translation table format support.

For the PAR we also need to correct the masking applied for
32 bit writes (there are no bits reserved if LPAE is implemented)
and clear the high half when doing a 32 bit result VA-to-PA
lookup.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-07-12 10:59:54 +00:00
..
arm-semi.c build: move obj-TARGET-y variables to nested Makefile.objs 2012-06-07 07:17:36 +02:00
cpu-qom.h target-arm: Convert cp15 crn=1 registers 2012-06-20 12:08:22 +00:00
cpu.c target-arm: Extend feature flags to 64 bits 2012-07-12 10:59:54 +00:00
cpu.h target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAE 2012-07-12 10:59:54 +00:00
helper.c target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAE 2012-07-12 10:59:54 +00:00
helper.h target-arm: Remove remaining old cp15 infrastructure 2012-06-20 12:13:04 +00:00
iwmmxt_helper.c target-arm: Don't overuse CPUState 2012-03-14 22:20:24 +01:00
machine.c target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAE 2012-07-12 10:59:54 +00:00
Makefile.objs build: move other target-*/ objects to nested Makefile.objs 2012-06-07 09:21:11 +02:00
neon_helper.c target-arm: When setting FPSCR.QC, don't clear other FPSCR bits 2012-05-10 12:56:08 +00:00
op_addsub.h Correct spelling of licensed 2011-07-23 11:26:12 -05:00
op_helper.c target-arm: initial coprocessor register framework 2012-06-20 12:01:02 +00:00
translate.c target-arm: Fix TCG temp handling in 64 bit cp writes 2012-07-12 10:59:53 +00:00