b4cb930e40
In this commit SPI shift engine and sequencer logic is implemented. Shift engine performs serialization and de-serialization according to the control by the sequencer and according to the setup defined in the configuration registers. Sequencer implements the main control logic and FSM to handle data transmit and data receive control of the shift engine. Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com> Reviewed-by: Caleb Schlossin <calebs@linux.vnet.ibm.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
134 lines
4.4 KiB
C
134 lines
4.4 KiB
C
/*
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* QEMU PowerPC SPI model
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*
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* Copyright (c) 2024, IBM Corporation.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef PNV_SPI_CONTROLLER_REGS_H
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#define PNV_SPI_CONTROLLER_REGS_H
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/*
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* Macros from target/ppc/cpu.h
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* These macros are copied from ppc target specific file target/ppc/cpu.h
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* as target/ppc/cpu.h cannot be included here.
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*/
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#define PPC_BIT(bit) (0x8000000000000000ULL >> (bit))
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#define PPC_BIT8(bit) (0x80 >> (bit))
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#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
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#define PPC_BITMASK8(bs, be) ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs))
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#define MASK_TO_LSH(m) (__builtin_ffsll(m) - 1)
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#define GETFIELD(m, v) (((v) & (m)) >> MASK_TO_LSH(m))
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#define SETFIELD(m, v, val) \
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(((v) & ~(m)) | ((((typeof(v))(val)) << MASK_TO_LSH(m)) & (m)))
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/* Error Register */
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#define ERROR_REG 0x00
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/* counter_config_reg */
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#define SPI_CTR_CFG_REG 0x01
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#define SPI_CTR_CFG_N1 PPC_BITMASK(0, 7)
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#define SPI_CTR_CFG_N2 PPC_BITMASK(8, 15)
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#define SPI_CTR_CFG_CMP1 PPC_BITMASK(24, 31)
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#define SPI_CTR_CFG_CMP2 PPC_BITMASK(32, 39)
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#define SPI_CTR_CFG_N1_CTRL_B1 PPC_BIT(49)
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#define SPI_CTR_CFG_N1_CTRL_B2 PPC_BIT(50)
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#define SPI_CTR_CFG_N1_CTRL_B3 PPC_BIT(51)
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#define SPI_CTR_CFG_N2_CTRL_B0 PPC_BIT(52)
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#define SPI_CTR_CFG_N2_CTRL_B1 PPC_BIT(53)
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#define SPI_CTR_CFG_N2_CTRL_B2 PPC_BIT(54)
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#define SPI_CTR_CFG_N2_CTRL_B3 PPC_BIT(55)
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/* config_reg */
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#define CONFIG_REG1 0x02
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/* clock_config_reset_control_ecc_enable_reg */
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#define SPI_CLK_CFG_REG 0x03
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#define SPI_CLK_CFG_HARD_RST 0x0084000000000000;
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#define SPI_CLK_CFG_RST_CTRL PPC_BITMASK(24, 27)
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#define SPI_CLK_CFG_ECC_EN PPC_BIT(28)
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#define SPI_CLK_CFG_ECC_CTRL PPC_BITMASK(29, 30)
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/* memory_mapping_reg */
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#define SPI_MM_REG 0x04
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#define SPI_MM_RDR_MATCH_VAL PPC_BITMASK(32, 47)
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#define SPI_MM_RDR_MATCH_MASK PPC_BITMASK(48, 63)
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/* transmit_data_reg */
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#define SPI_XMIT_DATA_REG 0x05
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/* receive_data_reg */
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#define SPI_RCV_DATA_REG 0x06
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/* sequencer_operation_reg */
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#define SPI_SEQ_OP_REG 0x07
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/* status_reg */
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#define SPI_STS_REG 0x08
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#define SPI_STS_RDR_FULL PPC_BIT(0)
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#define SPI_STS_RDR_OVERRUN PPC_BIT(1)
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#define SPI_STS_RDR_UNDERRUN PPC_BIT(2)
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#define SPI_STS_TDR_FULL PPC_BIT(4)
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#define SPI_STS_TDR_OVERRUN PPC_BIT(5)
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#define SPI_STS_TDR_UNDERRUN PPC_BIT(6)
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#define SPI_STS_SEQ_FSM PPC_BITMASK(8, 15)
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#define SPI_STS_SHIFTER_FSM PPC_BITMASK(16, 27)
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#define SPI_STS_SEQ_INDEX PPC_BITMASK(28, 31)
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#define SPI_STS_GEN_STATUS_B3 PPC_BIT(35)
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#define SPI_STS_RDR PPC_BITMASK(1, 3)
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#define SPI_STS_TDR PPC_BITMASK(5, 7)
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/*
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* Shifter states
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*
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* These are the same values defined for the Shifter FSM field of the
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* status register. It's a 12 bit field so we will represent it as three
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* nibbles in the constants.
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*
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* These are shifter_fsm values
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*
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* Status reg bits 16-27 -> field bits 0-11
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* bits 0,1,2,5 unused/reserved
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* bit 4 crc shift in (unused)
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* bit 8 crc shift out (unused)
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*/
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#define FSM_DONE 0x100 /* bit 3 */
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#define FSM_SHIFT_N2 0x020 /* bit 6 */
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#define FSM_WAIT 0x010 /* bit 7 */
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#define FSM_SHIFT_N1 0x004 /* bit 9 */
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#define FSM_START 0x002 /* bit 10 */
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#define FSM_IDLE 0x001 /* bit 11 */
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/*
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* Sequencer states
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*
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* These are sequencer_fsm values
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*
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* Status reg bits 8-15 -> field bits 0-7
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* bits 0-3 unused/reserved
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*
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*/
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#define SEQ_STATE_INDEX_INCREMENT 0x08 /* bit 4 */
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#define SEQ_STATE_EXECUTE 0x04 /* bit 5 */
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#define SEQ_STATE_DECODE 0x02 /* bit 6 */
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#define SEQ_STATE_IDLE 0x01 /* bit 7 */
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/*
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* These are the supported sequencer operations.
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* Only the upper nibble is significant because for many operations
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* the lower nibble is a variable specific to the operation.
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*/
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#define SEQ_OP_STOP 0x00
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#define SEQ_OP_SELECT_SLAVE 0x10
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#define SEQ_OP_SHIFT_N1 0x30
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#define SEQ_OP_SHIFT_N2 0x40
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#define SEQ_OP_BRANCH_IFNEQ_RDR 0x60
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#define SEQ_OP_TRANSFER_TDR 0xC0
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#define SEQ_OP_BRANCH_IFNEQ_INC_1 0xE0
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#define SEQ_OP_BRANCH_IFNEQ_INC_2 0xF0
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#define NUM_SEQ_OPS 8
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#endif
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