a031ac6161
Define a bit for MXU in insn_flags. This is the first non-MIPS (third party) ASE supported in QEMU for MIPS, so it is placed in the section "bits 56-63: vendor-specific ASEs". Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Craig Janeczek <jancraig@amazon.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
115 lines
3.8 KiB
C
115 lines
3.8 KiB
C
#ifndef QEMU_MIPS_DEFS_H
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#define QEMU_MIPS_DEFS_H
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/* If we want to use host float regs... */
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//#define USE_HOST_FLOAT_REGS
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/* Real pages are variable size... */
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#define TARGET_PAGE_BITS 12
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#define MIPS_TLB_MAX 128
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#if defined(TARGET_MIPS64)
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#define TARGET_LONG_BITS 64
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#define TARGET_PHYS_ADDR_SPACE_BITS 48
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#define TARGET_VIRT_ADDR_SPACE_BITS 48
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#else
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#define TARGET_LONG_BITS 32
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#define TARGET_PHYS_ADDR_SPACE_BITS 40
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# ifdef CONFIG_USER_ONLY
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# define TARGET_VIRT_ADDR_SPACE_BITS 31
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# else
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# define TARGET_VIRT_ADDR_SPACE_BITS 32
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#endif
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#endif
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/*
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* bit definitions for insn_flags (ISAs/ASEs flags)
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* ------------------------------------------------
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*/
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/*
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* bits 0-31: MIPS base instruction sets
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*/
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#define ISA_MIPS1 0x0000000000000001ULL
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#define ISA_MIPS2 0x0000000000000002ULL
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#define ISA_MIPS3 0x0000000000000004ULL
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#define ISA_MIPS4 0x0000000000000008ULL
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#define ISA_MIPS5 0x0000000000000010ULL
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#define ISA_MIPS32 0x0000000000000020ULL
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#define ISA_MIPS32R2 0x0000000000000040ULL
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#define ISA_MIPS64 0x0000000000000080ULL
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#define ISA_MIPS64R2 0x0000000000000100ULL
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#define ISA_MIPS32R3 0x0000000000000200ULL
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#define ISA_MIPS64R3 0x0000000000000400ULL
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#define ISA_MIPS32R5 0x0000000000000800ULL
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#define ISA_MIPS64R5 0x0000000000001000ULL
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#define ISA_MIPS32R6 0x0000000000002000ULL
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#define ISA_MIPS64R6 0x0000000000004000ULL
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#define ISA_NANOMIPS32 0x0000000000008000ULL
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/*
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* bits 32-47: MIPS ASEs
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*/
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#define ASE_MIPS16 0x0000000100000000ULL
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#define ASE_MIPS3D 0x0000000200000000ULL
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#define ASE_MDMX 0x0000000400000000ULL
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#define ASE_DSP 0x0000000800000000ULL
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#define ASE_DSP_R2 0x0000001000000000ULL
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#define ASE_DSP_R3 0x0000002000000000ULL
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#define ASE_MT 0x0000004000000000ULL
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#define ASE_SMARTMIPS 0x0000008000000000ULL
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#define ASE_MICROMIPS 0x0000010000000000ULL
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#define ASE_MSA 0x0000020000000000ULL
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/*
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* bits 48-55: vendor-specific base instruction sets
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*/
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#define INSN_LOONGSON2E 0x0001000000000000ULL
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#define INSN_LOONGSON2F 0x0002000000000000ULL
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#define INSN_VR54XX 0x0004000000000000ULL
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#define INSN_R5900 0x0008000000000000ULL
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/*
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* bits 56-63: vendor-specific ASEs
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*/
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#define ASE_MMI 0x0100000000000000ULL
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#define ASE_MXU 0x0200000000000000ULL
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/* MIPS CPU defines. */
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#define CPU_MIPS1 (ISA_MIPS1)
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#define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2)
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#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3)
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#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4)
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#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX)
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#define CPU_R5900 (CPU_MIPS3 | INSN_R5900)
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#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E)
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#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F)
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#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
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/* MIPS Technologies "Release 1" */
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#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32)
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#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64)
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/* MIPS Technologies "Release 2" */
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#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2)
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#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
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/* MIPS Technologies "Release 3" */
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#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
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#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3)
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/* MIPS Technologies "Release 5" */
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#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
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#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5)
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/* MIPS Technologies "Release 6" */
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#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6)
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#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6)
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/* Wave Computing: "nanoMIPS" */
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#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32)
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/* Strictly follow the architecture standard:
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- Disallow "special" instruction handling for PMON/SPIM.
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Note that we still maintain Count/Compare to match the host clock. */
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//#define MIPS_STRICT_STANDARD 1
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#endif /* QEMU_MIPS_DEFS_H */
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