10a8f7d25a
On LoongArch physical machine, one extioi interrupt controller only supports 4 cpus. With processor more than 4 cpus, there are multiple extioi interrupt controllers; if interrupts need to be routed to other cpus, they are forwarded from extioi node0 to other extioi nodes. On virt machine model, there is simple extioi interrupt device model. All cpus can access register of extioi interrupt controller, however interrupt can only be route to 4 vcpu for compatible with old kernel. This patch adds dynamic cpu number support about extioi interrupt. With old kernel legacy extioi model is used, however kernel can detect and choose new route method in future, so that interrupt can be routed to all vcpus. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20231215100333.3933632-4-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
69 lines
2.5 KiB
C
69 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* LoongArch 3A5000 ext interrupt controller definitions
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*
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* Copyright (C) 2021 Loongson Technology Corporation Limited
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*/
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#include "hw/sysbus.h"
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#include "hw/loongarch/virt.h"
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#ifndef LOONGARCH_EXTIOI_H
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#define LOONGARCH_EXTIOI_H
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#define LS3A_INTC_IP 8
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#define EXTIOI_IRQS (256)
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#define EXTIOI_IRQS_BITMAP_SIZE (256 / 8)
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/* irq from EXTIOI is routed to no more than 4 cpus */
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#define EXTIOI_CPUS (4)
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/* map to ipnum per 32 irqs */
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#define EXTIOI_IRQS_IPMAP_SIZE (256 / 32)
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#define EXTIOI_IRQS_COREMAP_SIZE 256
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#define EXTIOI_IRQS_NODETYPE_COUNT 16
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#define EXTIOI_IRQS_GROUP_COUNT 8
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#define APIC_OFFSET 0x400
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#define APIC_BASE (0x1000ULL + APIC_OFFSET)
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#define EXTIOI_NODETYPE_START (0x4a0 - APIC_OFFSET)
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#define EXTIOI_NODETYPE_END (0x4c0 - APIC_OFFSET)
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#define EXTIOI_IPMAP_START (0x4c0 - APIC_OFFSET)
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#define EXTIOI_IPMAP_END (0x4c8 - APIC_OFFSET)
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#define EXTIOI_ENABLE_START (0x600 - APIC_OFFSET)
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#define EXTIOI_ENABLE_END (0x620 - APIC_OFFSET)
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#define EXTIOI_BOUNCE_START (0x680 - APIC_OFFSET)
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#define EXTIOI_BOUNCE_END (0x6a0 - APIC_OFFSET)
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#define EXTIOI_ISR_START (0x700 - APIC_OFFSET)
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#define EXTIOI_ISR_END (0x720 - APIC_OFFSET)
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#define EXTIOI_COREISR_START (0x800 - APIC_OFFSET)
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#define EXTIOI_COREISR_END (0xB20 - APIC_OFFSET)
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#define EXTIOI_COREMAP_START (0xC00 - APIC_OFFSET)
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#define EXTIOI_COREMAP_END (0xD00 - APIC_OFFSET)
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typedef struct ExtIOICore {
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uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT];
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DECLARE_BITMAP(sw_isr[LS3A_INTC_IP], EXTIOI_IRQS);
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qemu_irq parent_irq[LS3A_INTC_IP];
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} ExtIOICore;
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#define TYPE_LOONGARCH_EXTIOI "loongarch.extioi"
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OBJECT_DECLARE_SIMPLE_TYPE(LoongArchExtIOI, LOONGARCH_EXTIOI)
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struct LoongArchExtIOI {
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SysBusDevice parent_obj;
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uint32_t num_cpu;
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/* hardware state */
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uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2];
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uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT];
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uint32_t isr[EXTIOI_IRQS / 32];
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uint32_t enable[EXTIOI_IRQS / 32];
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uint32_t ipmap[EXTIOI_IRQS_IPMAP_SIZE / 4];
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uint32_t coremap[EXTIOI_IRQS / 4];
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uint32_t sw_pending[EXTIOI_IRQS / 32];
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uint8_t sw_ipmap[EXTIOI_IRQS_IPMAP_SIZE];
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uint8_t sw_coremap[EXTIOI_IRQS];
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qemu_irq irq[EXTIOI_IRQS];
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ExtIOICore *cpu;
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MemoryRegion extioi_system_mem;
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};
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#endif /* LOONGARCH_EXTIOI_H */
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