da71b7e3ed
The XIVE2 interrupt controller of the POWER10 processor follows the
same logic than on POWER9 but the HW interface has been largely
reviewed. It has a new register interface, different BARs, extra
VSDs, new layout for the XIVE2 structures, and a set of new features
which are described below.
This is a model of the POWER10 XIVE2 interrupt controller for the
PowerNV machine. It focuses primarily on the needs of the skiboot
firmware but some initial hypervisor support is implemented for KVM
use (escalation).
Support for new features will be implemented in time and will require
new support from the OS.
* XIVE2 BARS
The interrupt controller BARs have a different layout outlined below.
Each sub-engine has now own its range and the indirect TIMA access was
replaced with a set of pages, one per CPU, under the IC BAR:
- IC BAR (Interrupt Controller)
. 4 pages, one per sub-engine
. 128 indirect TIMA pages
- TM BAR (Thread Interrupt Management Area)
. 4 pages
- ESB BAR (ESB pages for IPIs)
. up to 1TB
- END BAR (ESB pages for ENDs)
. up to 2TB
- NVC BAR (Notification Virtual Crowd)
. up to 128
- NVPG BAR (Notification Virtual Process and Group)
. up to 1TB
- Direct mapped Thread Context Area (reads & writes)
OPAL does not use the grouping and crowd capability.
* Virtual Structure Tables
XIVE2 adds new tables types and also changes the field layout of the END
and NVP Virtualization Structure Descriptors.
- EAS
- END new layout
- NVT was splitted in :
. NVP (Processor), 32B
. NVG (Group), 32B
. NVC (Crowd == P9 block group) 32B
- IC for remote configuration
- SYNC for cache injection
- ERQ for event input queue
The setup is slighly different on XIVE2 because the indexing has changed
for some of the tables, block ID or the chip topology ID can be used.
* XIVE2 features
SCOM and MMIO registers have a new layout and XIVE2 adds a new global
capability and configuration registers.
The lowlevel hardware offers a set of new features among which :
- a configurable number of priorities : 1 - 8
- StoreEOI with load-after-store ordering is activated by default
- Gen2 TIMA layout
- A P9-compat mode, or Gen1, TIMA toggle bit for SW compatibility
- increase to 24bit for VP number
Other features will have some impact on the Hypervisor and guest OS
when activated, but this is not required for initial support of the
controller.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
170 lines
4.2 KiB
C
170 lines
4.2 KiB
C
/*
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* QEMU PowerPC XIVE interrupt controller model
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*
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* Copyright (c) 2017-2019, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#ifndef PPC_PNV_XIVE_H
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#define PPC_PNV_XIVE_H
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#include "hw/ppc/xive.h"
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#include "qom/object.h"
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#include "hw/ppc/xive2.h"
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struct PnvChip;
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#define TYPE_PNV_XIVE "pnv-xive"
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OBJECT_DECLARE_TYPE(PnvXive, PnvXiveClass,
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PNV_XIVE)
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#define XIVE_BLOCK_MAX 16
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#define XIVE_TABLE_BLK_MAX 16 /* Block Scope Table (0-15) */
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#define XIVE_TABLE_MIG_MAX 16 /* Migration Register Table (1-15) */
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#define XIVE_TABLE_VDT_MAX 16 /* VDT Domain Table (0-15) */
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#define XIVE_TABLE_EDT_MAX 64 /* EDT Domain Table (0-63) */
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struct PnvXive {
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XiveRouter parent_obj;
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/* Owning chip */
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struct PnvChip *chip;
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/* XSCOM addresses giving access to the controller registers */
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MemoryRegion xscom_regs;
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/* Main MMIO regions that can be configured by FW */
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MemoryRegion ic_mmio;
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MemoryRegion ic_reg_mmio;
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MemoryRegion ic_notify_mmio;
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MemoryRegion ic_lsi_mmio;
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MemoryRegion tm_indirect_mmio;
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MemoryRegion vc_mmio;
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MemoryRegion pc_mmio;
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MemoryRegion tm_mmio;
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/*
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* IPI and END address spaces modeling the EDT segmentation in the
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* VC region
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*/
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AddressSpace ipi_as;
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MemoryRegion ipi_mmio;
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MemoryRegion ipi_edt_mmio;
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AddressSpace end_as;
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MemoryRegion end_mmio;
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MemoryRegion end_edt_mmio;
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/* Shortcut values for the Main MMIO regions */
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hwaddr ic_base;
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uint32_t ic_shift;
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hwaddr vc_base;
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uint32_t vc_shift;
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hwaddr pc_base;
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uint32_t pc_shift;
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hwaddr tm_base;
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uint32_t tm_shift;
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/* Our XIVE source objects for IPIs and ENDs */
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XiveSource ipi_source;
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XiveENDSource end_source;
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/* Interrupt controller registers */
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uint64_t regs[0x300];
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/*
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* Virtual Structure Descriptor tables : EAT, SBE, ENDT, NVTT, IRQ
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* These are in a SRAM protected by ECC.
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*/
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uint64_t vsds[5][XIVE_BLOCK_MAX];
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/* Translation tables */
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uint64_t blk[XIVE_TABLE_BLK_MAX];
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uint64_t mig[XIVE_TABLE_MIG_MAX];
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uint64_t vdt[XIVE_TABLE_VDT_MAX];
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uint64_t edt[XIVE_TABLE_EDT_MAX];
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};
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struct PnvXiveClass {
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XiveRouterClass parent_class;
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DeviceRealize parent_realize;
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};
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void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon);
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/*
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* XIVE2 interrupt controller (POWER10)
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*/
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#define TYPE_PNV_XIVE2 "pnv-xive2"
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OBJECT_DECLARE_TYPE(PnvXive2, PnvXive2Class, PNV_XIVE2);
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typedef struct PnvXive2 {
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Xive2Router parent_obj;
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/* Owning chip */
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struct PnvChip *chip;
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/* XSCOM addresses giving access to the controller registers */
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MemoryRegion xscom_regs;
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MemoryRegion ic_mmio;
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MemoryRegion ic_mmios[8];
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MemoryRegion esb_mmio;
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MemoryRegion end_mmio;
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MemoryRegion nvc_mmio;
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MemoryRegion nvpg_mmio;
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MemoryRegion tm_mmio;
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/* Shortcut values for the Main MMIO regions */
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hwaddr ic_base;
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uint32_t ic_shift;
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hwaddr esb_base;
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uint32_t esb_shift;
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hwaddr end_base;
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uint32_t end_shift;
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hwaddr nvc_base;
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uint32_t nvc_shift;
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hwaddr nvpg_base;
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uint32_t nvpg_shift;
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hwaddr tm_base;
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uint32_t tm_shift;
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/* Interrupt controller registers */
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uint64_t cq_regs[0x40];
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uint64_t vc_regs[0x100];
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uint64_t pc_regs[0x100];
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uint64_t tctxt_regs[0x30];
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/* To change default behavior */
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uint64_t capabilities;
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uint64_t config;
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/* Our XIVE source objects for IPIs and ENDs */
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XiveSource ipi_source;
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Xive2EndSource end_source;
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/*
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* Virtual Structure Descriptor tables
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* These are in a SRAM protected by ECC.
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*/
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uint64_t vsds[9][XIVE_BLOCK_MAX];
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/* Translation tables */
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uint64_t tables[8][XIVE_BLOCK_MAX];
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} PnvXive2;
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typedef struct PnvXive2Class {
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Xive2RouterClass parent_class;
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DeviceRealize parent_realize;
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} PnvXive2Class;
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void pnv_xive2_pic_print_info(PnvXive2 *xive, Monitor *mon);
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#endif /* PPC_PNV_XIVE_H */
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