qemu/target/arm
Peter Maydell 85e7d1e9ff target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration
Architecturally, for an M-profile CPU with the LOB feature the
LTPSIZE field in FPDSCR is always constant 4.  QEMU's implementation
enforces this everywhere, except that we don't check that it is true
in incoming migration data.

We're going to add come in gen_update_fp_context() which relies on
the "always 4" property.  Since this is TCG-only, we don't actually
need to be robust to bogus incoming migration data, and the effect of
it being wrong would be wrong code generation rather than a QEMU
crash; but if it did ever happen somehow it would be very difficult
to track down the cause.  Add a check so that we fail the inbound
migration if the FPDSCR.LTPSIZE value is incorrect.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210913095440.13462-3-peter.maydell@linaro.org
2021-09-21 16:28:27 +01:00
..
hvf
a32-uncond.decode
a32.decode
arch_dump.c
arm_ldst.h
arm-powerctl.c
arm-powerctl.h
cpu64.c
cpu_tcg.c
cpu-param.h
cpu-qom.h
cpu.c
cpu.h
crypto_helper.c
debug_helper.c
gdbstub64.c
gdbstub.c
helper-a64.c
helper-a64.h
helper-mve.h
helper-sve.h
helper.c
helper.h
hvf_arm.h
idau.h
internals.h
iwmmxt_helper.c
Kconfig
kvm64.c
kvm_arm.h
kvm-consts.h
kvm-stub.c
kvm.c
m_helper.c
m-nocp.decode
machine.c target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration 2021-09-21 16:28:27 +01:00
meson.build
monitor.c
mte_helper.c
mve_helper.c
mve.decode
neon_helper.c
neon-dp.decode
neon-ls.decode
neon-shared.decode
op_addsub.h
op_helper.c
pauth_helper.c
psci.c
sve_helper.c
sve.decode
syndrome.h
t16.decode
t32.decode
tlb_helper.c
trace-events
trace.h
translate-a32.h
translate-a64.c
translate-a64.h
translate-m-nocp.c
translate-mve.c
translate-neon.c
translate-sve.c
translate-vfp.c
translate.c
translate.h
vec_helper.c
vec_internal.h
vfp_helper.c
vfp-uncond.decode
vfp.decode