Michael Clark 85ba724fd6 RISC-V: Allow setting and clearing multiple irqs ... Change the API of riscv_set_local_interrupt to take a write mask and value to allow setting and clearing of multiple local interrupts atomically in a single call. Rename the new function to riscv_cpu_update_mip. Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2018-10-17 13:02:09 -07:00
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cpu_bits.h	RISC-V: Improve page table walker spec compliance	2018-09-04 13:19:23 -07:00
cpu_user.h	RISC-V Linux User Emulation	2018-03-07 08:30:28 +13:00
cpu.c	target/riscv: Honor CPU_DUMP_FPU	2018-05-18 14:52:38 -07:00
cpu.h	RISC-V: Allow setting and clearing multiple irqs	2018-10-17 13:02:09 -07:00
fpu_helper.c	target/riscv: Remove floatX_maybe_silence_nan from conversions	2018-05-17 15:27:15 -07:00
gdbstub.c	RISC-V GDB Stub	2018-03-07 08:30:28 +13:00
helper.c	RISC-V: Simplify riscv_cpu_local_irqs_pending	2018-09-04 13:19:37 -07:00
helper.h	RISC-V CPU Helpers	2018-03-07 08:30:28 +13:00
instmap.h	RISC-V TCG Code Generation	2018-03-07 08:30:28 +13:00
Makefile.objs	RISC-V Build Infrastructure	2018-03-07 08:30:28 +13:00
op_helper.c	RISC-V: Allow setting and clearing multiple irqs	2018-10-17 13:02:09 -07:00
pmp.c	RISC-V Physical Memory Protection	2018-03-07 08:30:28 +13:00
pmp.h	RISC-V Physical Memory Protection	2018-03-07 08:30:28 +13:00
translate.c	target/riscv: call gen_goto_tb on DISAS_TOO_MANY	2018-09-05 09:58:38 -07:00