54e755588c
MIPS Jazz chipset doesn't seem to raise data bus exceptions on invalid accesses.
However, there is no easy way to prevent them. Creating a big memory region
for the whole address space doesn't prevent memory core to directly call
unassigned_mem_read/write which in turn call cpu->do_unassigned_access,
which (for MIPS CPU) raise an data bus exception.
This fixes a MIPS Jazz regression introduced in
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| .. | ||
| addr.c | ||
| cputimer.c | ||
| gt64xxx_pci.c | ||
| Makefile.objs | ||
| mips_fulong2e.c | ||
| mips_int.c | ||
| mips_jazz.c | ||
| mips_malta.c | ||
| mips_mipssim.c | ||
| mips_r4k.c | ||