83d7ed5c57
Jakub noticed[1] that, when using pin-based interrupts, the device will unconditionally deasssert when any CQEs are acknowledged. However, the pin should not be deasserted if other completion queues still holds unacknowledged CQEs. The bug is an artifact of commitca247d3509("hw/block/nvme: fix pin-based interrupt behavior") which fixed one bug but introduced another. This is the third time someone tries to fix pin-based interrupts (see commit5e9aa92eb1("hw/block: Fix pin-based interrupt behaviour of NVMe"))... Third time's the charm, so fix it, again, by keeping track of how many CQs have unacknowledged CQEs and only deassert when all are cleared. [1]: <20210610114624.304681-1-jakub.jermar@kernkonzept.com> Cc: qemu-stable@nongnu.org Fixes:ca247d3509("hw/block/nvme: fix pin-based interrupt behavior") Reported-by: Jakub Jermář <jakub.jermar@kernkonzept.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com> Reviewed-by: Keith Busch <kbusch@kernel.org>
555 lines
16 KiB
C
555 lines
16 KiB
C
/*
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* QEMU NVM Express
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*
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* Copyright (c) 2012 Intel Corporation
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* Copyright (c) 2021 Minwoo Im
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* Copyright (c) 2021 Samsung Electronics Co., Ltd.
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*
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* Authors:
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* Keith Busch <kbusch@kernel.org>
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* Klaus Jensen <k.jensen@samsung.com>
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* Gollu Appalanaidu <anaidu.gollu@samsung.com>
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* Dmitry Fomichev <dmitry.fomichev@wdc.com>
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* Minwoo Im <minwoo.im.dev@gmail.com>
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*
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* This code is licensed under the GNU GPL v2 or later.
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*/
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#ifndef HW_NVME_INTERNAL_H
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#define HW_NVME_INTERNAL_H
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#include "qemu/uuid.h"
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#include "hw/pci/pci.h"
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#include "hw/block/block.h"
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#include "block/nvme.h"
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#define NVME_MAX_CONTROLLERS 32
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#define NVME_MAX_NAMESPACES 256
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#define NVME_EUI64_DEFAULT ((uint64_t)0x5254000000000000)
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QEMU_BUILD_BUG_ON(NVME_MAX_NAMESPACES > NVME_NSID_BROADCAST - 1);
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typedef struct NvmeCtrl NvmeCtrl;
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typedef struct NvmeNamespace NvmeNamespace;
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#define TYPE_NVME_SUBSYS "nvme-subsys"
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#define NVME_SUBSYS(obj) \
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OBJECT_CHECK(NvmeSubsystem, (obj), TYPE_NVME_SUBSYS)
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typedef struct NvmeSubsystem {
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DeviceState parent_obj;
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uint8_t subnqn[256];
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NvmeCtrl *ctrls[NVME_MAX_CONTROLLERS];
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NvmeNamespace *namespaces[NVME_MAX_NAMESPACES + 1];
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struct {
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char *nqn;
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} params;
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} NvmeSubsystem;
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int nvme_subsys_register_ctrl(NvmeCtrl *n, Error **errp);
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static inline NvmeCtrl *nvme_subsys_ctrl(NvmeSubsystem *subsys,
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uint32_t cntlid)
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{
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if (!subsys || cntlid >= NVME_MAX_CONTROLLERS) {
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return NULL;
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}
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return subsys->ctrls[cntlid];
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}
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static inline NvmeNamespace *nvme_subsys_ns(NvmeSubsystem *subsys,
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uint32_t nsid)
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{
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if (!subsys || !nsid || nsid > NVME_MAX_NAMESPACES) {
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return NULL;
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}
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return subsys->namespaces[nsid];
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}
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#define TYPE_NVME_NS "nvme-ns"
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#define NVME_NS(obj) \
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OBJECT_CHECK(NvmeNamespace, (obj), TYPE_NVME_NS)
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typedef struct NvmeZone {
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NvmeZoneDescr d;
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uint64_t w_ptr;
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QTAILQ_ENTRY(NvmeZone) entry;
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} NvmeZone;
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typedef struct NvmeNamespaceParams {
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bool detached;
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bool shared;
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uint32_t nsid;
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QemuUUID uuid;
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uint64_t eui64;
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bool eui64_default;
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uint16_t ms;
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uint8_t mset;
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uint8_t pi;
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uint8_t pil;
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uint16_t mssrl;
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uint32_t mcl;
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uint8_t msrc;
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bool zoned;
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bool cross_zone_read;
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uint64_t zone_size_bs;
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uint64_t zone_cap_bs;
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uint32_t max_active_zones;
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uint32_t max_open_zones;
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uint32_t zd_extension_size;
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} NvmeNamespaceParams;
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typedef struct NvmeNamespace {
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DeviceState parent_obj;
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BlockConf blkconf;
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int32_t bootindex;
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int64_t size;
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int64_t moff;
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NvmeIdNs id_ns;
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NvmeLBAF lbaf;
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size_t lbasz;
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const uint32_t *iocs;
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uint8_t csi;
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uint16_t status;
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int attached;
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QTAILQ_ENTRY(NvmeNamespace) entry;
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NvmeIdNsZoned *id_ns_zoned;
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NvmeZone *zone_array;
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QTAILQ_HEAD(, NvmeZone) exp_open_zones;
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QTAILQ_HEAD(, NvmeZone) imp_open_zones;
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QTAILQ_HEAD(, NvmeZone) closed_zones;
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QTAILQ_HEAD(, NvmeZone) full_zones;
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uint32_t num_zones;
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uint64_t zone_size;
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uint64_t zone_capacity;
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uint32_t zone_size_log2;
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uint8_t *zd_extensions;
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int32_t nr_open_zones;
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int32_t nr_active_zones;
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NvmeNamespaceParams params;
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struct {
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uint32_t err_rec;
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} features;
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} NvmeNamespace;
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static inline uint32_t nvme_nsid(NvmeNamespace *ns)
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{
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if (ns) {
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return ns->params.nsid;
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}
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return 0;
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}
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static inline size_t nvme_l2b(NvmeNamespace *ns, uint64_t lba)
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{
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return lba << ns->lbaf.ds;
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}
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static inline size_t nvme_m2b(NvmeNamespace *ns, uint64_t lba)
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{
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return ns->lbaf.ms * lba;
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}
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static inline int64_t nvme_moff(NvmeNamespace *ns, uint64_t lba)
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{
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return ns->moff + nvme_m2b(ns, lba);
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}
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static inline bool nvme_ns_ext(NvmeNamespace *ns)
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{
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return !!NVME_ID_NS_FLBAS_EXTENDED(ns->id_ns.flbas);
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}
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static inline NvmeZoneState nvme_get_zone_state(NvmeZone *zone)
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{
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return zone->d.zs >> 4;
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}
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static inline void nvme_set_zone_state(NvmeZone *zone, NvmeZoneState state)
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{
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zone->d.zs = state << 4;
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}
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static inline uint64_t nvme_zone_rd_boundary(NvmeNamespace *ns, NvmeZone *zone)
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{
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return zone->d.zslba + ns->zone_size;
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}
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static inline uint64_t nvme_zone_wr_boundary(NvmeZone *zone)
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{
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return zone->d.zslba + zone->d.zcap;
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}
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static inline bool nvme_wp_is_valid(NvmeZone *zone)
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{
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uint8_t st = nvme_get_zone_state(zone);
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return st != NVME_ZONE_STATE_FULL &&
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st != NVME_ZONE_STATE_READ_ONLY &&
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st != NVME_ZONE_STATE_OFFLINE;
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}
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static inline uint8_t *nvme_get_zd_extension(NvmeNamespace *ns,
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uint32_t zone_idx)
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{
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return &ns->zd_extensions[zone_idx * ns->params.zd_extension_size];
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}
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static inline void nvme_aor_inc_open(NvmeNamespace *ns)
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{
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assert(ns->nr_open_zones >= 0);
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if (ns->params.max_open_zones) {
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ns->nr_open_zones++;
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assert(ns->nr_open_zones <= ns->params.max_open_zones);
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}
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}
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static inline void nvme_aor_dec_open(NvmeNamespace *ns)
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{
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if (ns->params.max_open_zones) {
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assert(ns->nr_open_zones > 0);
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ns->nr_open_zones--;
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}
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assert(ns->nr_open_zones >= 0);
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}
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static inline void nvme_aor_inc_active(NvmeNamespace *ns)
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{
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assert(ns->nr_active_zones >= 0);
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if (ns->params.max_active_zones) {
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ns->nr_active_zones++;
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assert(ns->nr_active_zones <= ns->params.max_active_zones);
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}
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}
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static inline void nvme_aor_dec_active(NvmeNamespace *ns)
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{
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if (ns->params.max_active_zones) {
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assert(ns->nr_active_zones > 0);
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ns->nr_active_zones--;
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assert(ns->nr_active_zones >= ns->nr_open_zones);
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}
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assert(ns->nr_active_zones >= 0);
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}
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void nvme_ns_init_format(NvmeNamespace *ns);
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int nvme_ns_setup(NvmeCtrl *n, NvmeNamespace *ns, Error **errp);
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void nvme_ns_drain(NvmeNamespace *ns);
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void nvme_ns_shutdown(NvmeNamespace *ns);
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void nvme_ns_cleanup(NvmeNamespace *ns);
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typedef struct NvmeAsyncEvent {
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QTAILQ_ENTRY(NvmeAsyncEvent) entry;
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NvmeAerResult result;
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} NvmeAsyncEvent;
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enum {
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NVME_SG_ALLOC = 1 << 0,
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NVME_SG_DMA = 1 << 1,
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};
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typedef struct NvmeSg {
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int flags;
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union {
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QEMUSGList qsg;
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QEMUIOVector iov;
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};
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} NvmeSg;
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typedef enum NvmeTxDirection {
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NVME_TX_DIRECTION_TO_DEVICE = 0,
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NVME_TX_DIRECTION_FROM_DEVICE = 1,
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} NvmeTxDirection;
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typedef struct NvmeRequest {
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struct NvmeSQueue *sq;
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struct NvmeNamespace *ns;
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BlockAIOCB *aiocb;
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uint16_t status;
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void *opaque;
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NvmeCqe cqe;
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NvmeCmd cmd;
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BlockAcctCookie acct;
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NvmeSg sg;
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QTAILQ_ENTRY(NvmeRequest)entry;
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} NvmeRequest;
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typedef struct NvmeBounceContext {
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NvmeRequest *req;
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struct {
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QEMUIOVector iov;
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uint8_t *bounce;
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} data, mdata;
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} NvmeBounceContext;
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static inline const char *nvme_adm_opc_str(uint8_t opc)
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{
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switch (opc) {
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case NVME_ADM_CMD_DELETE_SQ: return "NVME_ADM_CMD_DELETE_SQ";
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case NVME_ADM_CMD_CREATE_SQ: return "NVME_ADM_CMD_CREATE_SQ";
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case NVME_ADM_CMD_GET_LOG_PAGE: return "NVME_ADM_CMD_GET_LOG_PAGE";
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case NVME_ADM_CMD_DELETE_CQ: return "NVME_ADM_CMD_DELETE_CQ";
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case NVME_ADM_CMD_CREATE_CQ: return "NVME_ADM_CMD_CREATE_CQ";
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case NVME_ADM_CMD_IDENTIFY: return "NVME_ADM_CMD_IDENTIFY";
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case NVME_ADM_CMD_ABORT: return "NVME_ADM_CMD_ABORT";
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case NVME_ADM_CMD_SET_FEATURES: return "NVME_ADM_CMD_SET_FEATURES";
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case NVME_ADM_CMD_GET_FEATURES: return "NVME_ADM_CMD_GET_FEATURES";
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case NVME_ADM_CMD_ASYNC_EV_REQ: return "NVME_ADM_CMD_ASYNC_EV_REQ";
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case NVME_ADM_CMD_NS_ATTACHMENT: return "NVME_ADM_CMD_NS_ATTACHMENT";
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case NVME_ADM_CMD_FORMAT_NVM: return "NVME_ADM_CMD_FORMAT_NVM";
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default: return "NVME_ADM_CMD_UNKNOWN";
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}
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}
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static inline const char *nvme_io_opc_str(uint8_t opc)
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{
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switch (opc) {
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case NVME_CMD_FLUSH: return "NVME_NVM_CMD_FLUSH";
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case NVME_CMD_WRITE: return "NVME_NVM_CMD_WRITE";
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case NVME_CMD_READ: return "NVME_NVM_CMD_READ";
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case NVME_CMD_COMPARE: return "NVME_NVM_CMD_COMPARE";
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case NVME_CMD_WRITE_ZEROES: return "NVME_NVM_CMD_WRITE_ZEROES";
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case NVME_CMD_DSM: return "NVME_NVM_CMD_DSM";
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case NVME_CMD_VERIFY: return "NVME_NVM_CMD_VERIFY";
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case NVME_CMD_COPY: return "NVME_NVM_CMD_COPY";
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case NVME_CMD_ZONE_MGMT_SEND: return "NVME_ZONED_CMD_MGMT_SEND";
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case NVME_CMD_ZONE_MGMT_RECV: return "NVME_ZONED_CMD_MGMT_RECV";
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case NVME_CMD_ZONE_APPEND: return "NVME_ZONED_CMD_ZONE_APPEND";
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default: return "NVME_NVM_CMD_UNKNOWN";
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}
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}
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typedef struct NvmeSQueue {
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struct NvmeCtrl *ctrl;
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uint16_t sqid;
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uint16_t cqid;
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uint32_t head;
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uint32_t tail;
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uint32_t size;
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uint64_t dma_addr;
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QEMUTimer *timer;
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NvmeRequest *io_req;
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QTAILQ_HEAD(, NvmeRequest) req_list;
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QTAILQ_HEAD(, NvmeRequest) out_req_list;
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QTAILQ_ENTRY(NvmeSQueue) entry;
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} NvmeSQueue;
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typedef struct NvmeCQueue {
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struct NvmeCtrl *ctrl;
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uint8_t phase;
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uint16_t cqid;
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uint16_t irq_enabled;
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uint32_t head;
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uint32_t tail;
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uint32_t vector;
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uint32_t size;
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uint64_t dma_addr;
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QEMUTimer *timer;
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QTAILQ_HEAD(, NvmeSQueue) sq_list;
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QTAILQ_HEAD(, NvmeRequest) req_list;
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} NvmeCQueue;
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#define TYPE_NVME_BUS "nvme-bus"
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#define NVME_BUS(obj) OBJECT_CHECK(NvmeBus, (obj), TYPE_NVME_BUS)
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typedef struct NvmeBus {
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BusState parent_bus;
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} NvmeBus;
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#define TYPE_NVME "nvme"
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#define NVME(obj) \
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OBJECT_CHECK(NvmeCtrl, (obj), TYPE_NVME)
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typedef struct NvmeParams {
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char *serial;
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uint32_t num_queues; /* deprecated since 5.1 */
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uint32_t max_ioqpairs;
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uint16_t msix_qsize;
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uint32_t cmb_size_mb;
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uint8_t aerl;
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uint32_t aer_max_queued;
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uint8_t mdts;
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uint8_t vsl;
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bool use_intel_id;
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uint8_t zasl;
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bool auto_transition_zones;
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bool legacy_cmb;
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} NvmeParams;
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typedef struct NvmeCtrl {
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PCIDevice parent_obj;
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MemoryRegion bar0;
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MemoryRegion iomem;
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NvmeBar bar;
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NvmeParams params;
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NvmeBus bus;
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uint16_t cntlid;
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bool qs_created;
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uint32_t page_size;
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uint16_t page_bits;
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uint16_t max_prp_ents;
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uint16_t cqe_size;
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uint16_t sqe_size;
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uint32_t reg_size;
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uint32_t max_q_ents;
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uint8_t outstanding_aers;
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uint32_t irq_status;
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int cq_pending;
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uint64_t host_timestamp; /* Timestamp sent by the host */
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uint64_t timestamp_set_qemu_clock_ms; /* QEMU clock time */
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uint64_t starttime_ms;
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uint16_t temperature;
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uint8_t smart_critical_warning;
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struct {
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MemoryRegion mem;
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uint8_t *buf;
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bool cmse;
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hwaddr cba;
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} cmb;
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struct {
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HostMemoryBackend *dev;
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bool cmse;
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hwaddr cba;
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} pmr;
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uint8_t aer_mask;
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NvmeRequest **aer_reqs;
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QTAILQ_HEAD(, NvmeAsyncEvent) aer_queue;
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int aer_queued;
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uint32_t dmrsl;
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/* Namespace ID is started with 1 so bitmap should be 1-based */
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#define NVME_CHANGED_NSID_SIZE (NVME_MAX_NAMESPACES + 1)
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DECLARE_BITMAP(changed_nsids, NVME_CHANGED_NSID_SIZE);
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NvmeSubsystem *subsys;
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NvmeNamespace namespace;
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NvmeNamespace *namespaces[NVME_MAX_NAMESPACES + 1];
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NvmeSQueue **sq;
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NvmeCQueue **cq;
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NvmeSQueue admin_sq;
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NvmeCQueue admin_cq;
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NvmeIdCtrl id_ctrl;
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struct {
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struct {
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uint16_t temp_thresh_hi;
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uint16_t temp_thresh_low;
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};
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uint32_t async_config;
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} features;
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} NvmeCtrl;
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static inline NvmeNamespace *nvme_ns(NvmeCtrl *n, uint32_t nsid)
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{
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if (!nsid || nsid > NVME_MAX_NAMESPACES) {
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return NULL;
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}
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return n->namespaces[nsid];
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}
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static inline NvmeCQueue *nvme_cq(NvmeRequest *req)
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{
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NvmeSQueue *sq = req->sq;
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NvmeCtrl *n = sq->ctrl;
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return n->cq[sq->cqid];
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}
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static inline NvmeCtrl *nvme_ctrl(NvmeRequest *req)
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{
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NvmeSQueue *sq = req->sq;
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return sq->ctrl;
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}
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static inline uint16_t nvme_cid(NvmeRequest *req)
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{
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if (!req) {
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return 0xffff;
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}
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return le16_to_cpu(req->cqe.cid);
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}
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void nvme_attach_ns(NvmeCtrl *n, NvmeNamespace *ns);
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uint16_t nvme_bounce_data(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
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NvmeTxDirection dir, NvmeRequest *req);
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uint16_t nvme_bounce_mdata(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
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NvmeTxDirection dir, NvmeRequest *req);
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void nvme_rw_complete_cb(void *opaque, int ret);
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uint16_t nvme_map_dptr(NvmeCtrl *n, NvmeSg *sg, size_t len,
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NvmeCmd *cmd);
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/* from Linux kernel (crypto/crct10dif_common.c) */
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static const uint16_t t10_dif_crc_table[256] = {
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0x0000, 0x8BB7, 0x9CD9, 0x176E, 0xB205, 0x39B2, 0x2EDC, 0xA56B,
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0xEFBD, 0x640A, 0x7364, 0xF8D3, 0x5DB8, 0xD60F, 0xC161, 0x4AD6,
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0x54CD, 0xDF7A, 0xC814, 0x43A3, 0xE6C8, 0x6D7F, 0x7A11, 0xF1A6,
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0xBB70, 0x30C7, 0x27A9, 0xAC1E, 0x0975, 0x82C2, 0x95AC, 0x1E1B,
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0xA99A, 0x222D, 0x3543, 0xBEF4, 0x1B9F, 0x9028, 0x8746, 0x0CF1,
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0x4627, 0xCD90, 0xDAFE, 0x5149, 0xF422, 0x7F95, 0x68FB, 0xE34C,
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0xFD57, 0x76E0, 0x618E, 0xEA39, 0x4F52, 0xC4E5, 0xD38B, 0x583C,
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0x12EA, 0x995D, 0x8E33, 0x0584, 0xA0EF, 0x2B58, 0x3C36, 0xB781,
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0xD883, 0x5334, 0x445A, 0xCFED, 0x6A86, 0xE131, 0xF65F, 0x7DE8,
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0x373E, 0xBC89, 0xABE7, 0x2050, 0x853B, 0x0E8C, 0x19E2, 0x9255,
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0x8C4E, 0x07F9, 0x1097, 0x9B20, 0x3E4B, 0xB5FC, 0xA292, 0x2925,
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0x63F3, 0xE844, 0xFF2A, 0x749D, 0xD1F6, 0x5A41, 0x4D2F, 0xC698,
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0x7119, 0xFAAE, 0xEDC0, 0x6677, 0xC31C, 0x48AB, 0x5FC5, 0xD472,
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0x9EA4, 0x1513, 0x027D, 0x89CA, 0x2CA1, 0xA716, 0xB078, 0x3BCF,
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0x25D4, 0xAE63, 0xB90D, 0x32BA, 0x97D1, 0x1C66, 0x0B08, 0x80BF,
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0xCA69, 0x41DE, 0x56B0, 0xDD07, 0x786C, 0xF3DB, 0xE4B5, 0x6F02,
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0x3AB1, 0xB106, 0xA668, 0x2DDF, 0x88B4, 0x0303, 0x146D, 0x9FDA,
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|
0xD50C, 0x5EBB, 0x49D5, 0xC262, 0x6709, 0xECBE, 0xFBD0, 0x7067,
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|
0x6E7C, 0xE5CB, 0xF2A5, 0x7912, 0xDC79, 0x57CE, 0x40A0, 0xCB17,
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|
0x81C1, 0x0A76, 0x1D18, 0x96AF, 0x33C4, 0xB873, 0xAF1D, 0x24AA,
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|
0x932B, 0x189C, 0x0FF2, 0x8445, 0x212E, 0xAA99, 0xBDF7, 0x3640,
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|
0x7C96, 0xF721, 0xE04F, 0x6BF8, 0xCE93, 0x4524, 0x524A, 0xD9FD,
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|
0xC7E6, 0x4C51, 0x5B3F, 0xD088, 0x75E3, 0xFE54, 0xE93A, 0x628D,
|
|
0x285B, 0xA3EC, 0xB482, 0x3F35, 0x9A5E, 0x11E9, 0x0687, 0x8D30,
|
|
0xE232, 0x6985, 0x7EEB, 0xF55C, 0x5037, 0xDB80, 0xCCEE, 0x4759,
|
|
0x0D8F, 0x8638, 0x9156, 0x1AE1, 0xBF8A, 0x343D, 0x2353, 0xA8E4,
|
|
0xB6FF, 0x3D48, 0x2A26, 0xA191, 0x04FA, 0x8F4D, 0x9823, 0x1394,
|
|
0x5942, 0xD2F5, 0xC59B, 0x4E2C, 0xEB47, 0x60F0, 0x779E, 0xFC29,
|
|
0x4BA8, 0xC01F, 0xD771, 0x5CC6, 0xF9AD, 0x721A, 0x6574, 0xEEC3,
|
|
0xA415, 0x2FA2, 0x38CC, 0xB37B, 0x1610, 0x9DA7, 0x8AC9, 0x017E,
|
|
0x1F65, 0x94D2, 0x83BC, 0x080B, 0xAD60, 0x26D7, 0x31B9, 0xBA0E,
|
|
0xF0D8, 0x7B6F, 0x6C01, 0xE7B6, 0x42DD, 0xC96A, 0xDE04, 0x55B3
|
|
};
|
|
|
|
uint16_t nvme_check_prinfo(NvmeNamespace *ns, uint8_t prinfo, uint64_t slba,
|
|
uint32_t reftag);
|
|
uint16_t nvme_dif_mangle_mdata(NvmeNamespace *ns, uint8_t *mbuf, size_t mlen,
|
|
uint64_t slba);
|
|
void nvme_dif_pract_generate_dif(NvmeNamespace *ns, uint8_t *buf, size_t len,
|
|
uint8_t *mbuf, size_t mlen, uint16_t apptag,
|
|
uint32_t *reftag);
|
|
uint16_t nvme_dif_check(NvmeNamespace *ns, uint8_t *buf, size_t len,
|
|
uint8_t *mbuf, size_t mlen, uint8_t prinfo,
|
|
uint64_t slba, uint16_t apptag,
|
|
uint16_t appmask, uint32_t *reftag);
|
|
uint16_t nvme_dif_rw(NvmeCtrl *n, NvmeRequest *req);
|
|
|
|
|
|
#endif /* HW_NVME_INTERNAL_H */
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