a489d1951c
This converts existing DECLARE_OBJ_CHECKERS usage to OBJECT_DECLARE_TYPE when possible. $ ./scripts/codeconverter/converter.py -i \ --pattern=AddObjectDeclareType $(git grep -l '' -- '*.[ch]') Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Acked-by: Paul Durrant <paul@xen.org> Message-Id: <20200916182519.415636-5-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
57 lines
1.5 KiB
C
57 lines
1.5 KiB
C
/*
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* ASPEED SDRAM Memory Controller
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*
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* Copyright (C) 2016 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#ifndef ASPEED_SDMC_H
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#define ASPEED_SDMC_H
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#include "hw/sysbus.h"
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#include "qom/object.h"
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#define TYPE_ASPEED_SDMC "aspeed.sdmc"
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OBJECT_DECLARE_TYPE(AspeedSDMCState, AspeedSDMCClass, ASPEED_SDMC)
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#define TYPE_ASPEED_2400_SDMC TYPE_ASPEED_SDMC "-ast2400"
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#define TYPE_ASPEED_2500_SDMC TYPE_ASPEED_SDMC "-ast2500"
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#define TYPE_ASPEED_2600_SDMC TYPE_ASPEED_SDMC "-ast2600"
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/*
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* SDMC has 174 documented registers. In addition the u-boot device tree
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* describes the following regions:
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* - PHY status regs at offset 0x400, length 0x200
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* - PHY setting regs at offset 0x100, length 0x300
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*
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* There are two sets of MRS (Mode Registers) configuration in ast2600 memory
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* system: one is in the SDRAM MC (memory controller) which is used in run
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* time, and the other is in the DDR-PHY IP which is used during DDR-PHY
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* training.
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*/
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#define ASPEED_SDMC_NR_REGS (0x500 >> 2)
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struct AspeedSDMCState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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uint32_t regs[ASPEED_SDMC_NR_REGS];
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uint64_t ram_size;
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uint64_t max_ram_size;
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};
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struct AspeedSDMCClass {
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SysBusDeviceClass parent_class;
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uint64_t max_ram_size;
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const uint64_t *valid_ram_sizes;
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uint32_t (*compute_conf)(AspeedSDMCState *s, uint32_t data);
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void (*write)(AspeedSDMCState *s, uint32_t reg, uint32_t data);
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};
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#endif /* ASPEED_SDMC_H */
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