5cd8cadae8
We create optional sections with this patch. But we already have optional subsections. Instead of having two mechanism that do the same, we can just generalize it. For subsections we just change: - Add a needed function to VMStateDescription - Remove VMStateSubsection (after removal of the needed function it is just a VMStateDescription) - Adjust the whole tree, moving the needed function to the corresponding VMStateDescription Signed-off-by: Juan Quintela <quintela@redhat.com>
457 lines
12 KiB
C
457 lines
12 KiB
C
/*
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* APIC support - common bits of emulated and KVM kernel model
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*
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* Copyright (c) 2004-2005 Fabrice Bellard
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* Copyright (c) 2011 Jan Kiszka, Siemens AG
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*/
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#include "hw/i386/apic.h"
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#include "hw/i386/apic_internal.h"
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#include "trace.h"
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#include "sysemu/kvm.h"
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#include "hw/qdev.h"
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#include "hw/sysbus.h"
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static int apic_irq_delivered;
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bool apic_report_tpr_access;
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void cpu_set_apic_base(DeviceState *dev, uint64_t val)
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{
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trace_cpu_set_apic_base(val);
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if (dev) {
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APICCommonState *s = APIC_COMMON(dev);
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APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
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info->set_base(s, val);
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}
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}
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uint64_t cpu_get_apic_base(DeviceState *dev)
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{
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if (dev) {
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APICCommonState *s = APIC_COMMON(dev);
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trace_cpu_get_apic_base((uint64_t)s->apicbase);
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return s->apicbase;
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} else {
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trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP);
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return MSR_IA32_APICBASE_BSP;
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}
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}
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void cpu_set_apic_tpr(DeviceState *dev, uint8_t val)
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{
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APICCommonState *s;
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APICCommonClass *info;
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if (!dev) {
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return;
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}
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s = APIC_COMMON(dev);
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info = APIC_COMMON_GET_CLASS(s);
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info->set_tpr(s, val);
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}
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uint8_t cpu_get_apic_tpr(DeviceState *dev)
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{
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APICCommonState *s;
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APICCommonClass *info;
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if (!dev) {
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return 0;
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}
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s = APIC_COMMON(dev);
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info = APIC_COMMON_GET_CLASS(s);
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return info->get_tpr(s);
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}
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void apic_enable_tpr_access_reporting(DeviceState *dev, bool enable)
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{
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APICCommonState *s = APIC_COMMON(dev);
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APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
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apic_report_tpr_access = enable;
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if (info->enable_tpr_reporting) {
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info->enable_tpr_reporting(s, enable);
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}
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}
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void apic_enable_vapic(DeviceState *dev, hwaddr paddr)
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{
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APICCommonState *s = APIC_COMMON(dev);
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APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
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s->vapic_paddr = paddr;
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info->vapic_base_update(s);
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}
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void apic_handle_tpr_access_report(DeviceState *dev, target_ulong ip,
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TPRAccess access)
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{
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APICCommonState *s = APIC_COMMON(dev);
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vapic_report_tpr_access(s->vapic, CPU(s->cpu), ip, access);
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}
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void apic_report_irq_delivered(int delivered)
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{
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apic_irq_delivered += delivered;
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trace_apic_report_irq_delivered(apic_irq_delivered);
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}
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void apic_reset_irq_delivered(void)
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{
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/* Copy this into a local variable to encourage gcc to emit a plain
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* register for a sys/sdt.h marker. For details on this workaround, see:
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* https://sourceware.org/bugzilla/show_bug.cgi?id=13296
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*/
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volatile int a_i_d = apic_irq_delivered;
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trace_apic_reset_irq_delivered(a_i_d);
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apic_irq_delivered = 0;
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}
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int apic_get_irq_delivered(void)
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{
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trace_apic_get_irq_delivered(apic_irq_delivered);
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return apic_irq_delivered;
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}
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void apic_deliver_nmi(DeviceState *dev)
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{
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APICCommonState *s = APIC_COMMON(dev);
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APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
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info->external_nmi(s);
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}
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bool apic_next_timer(APICCommonState *s, int64_t current_time)
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{
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int64_t d;
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/* We need to store the timer state separately to support APIC
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* implementations that maintain a non-QEMU timer, e.g. inside the
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* host kernel. This open-coded state allows us to migrate between
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* both models. */
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s->timer_expiry = -1;
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if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) {
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return false;
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}
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d = (current_time - s->initial_count_load_time) >> s->count_shift;
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if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
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if (!s->initial_count) {
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return false;
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}
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d = ((d / ((uint64_t)s->initial_count + 1)) + 1) *
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((uint64_t)s->initial_count + 1);
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} else {
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if (d >= s->initial_count) {
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return false;
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}
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d = (uint64_t)s->initial_count + 1;
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}
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s->next_time = s->initial_count_load_time + (d << s->count_shift);
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s->timer_expiry = s->next_time;
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return true;
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}
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void apic_init_reset(DeviceState *dev)
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{
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APICCommonState *s;
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APICCommonClass *info;
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int i;
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if (!dev) {
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return;
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}
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s = APIC_COMMON(dev);
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s->tpr = 0;
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s->spurious_vec = 0xff;
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s->log_dest = 0;
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s->dest_mode = 0xf;
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memset(s->isr, 0, sizeof(s->isr));
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memset(s->tmr, 0, sizeof(s->tmr));
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memset(s->irr, 0, sizeof(s->irr));
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for (i = 0; i < APIC_LVT_NB; i++) {
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s->lvt[i] = APIC_LVT_MASKED;
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}
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s->esr = 0;
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memset(s->icr, 0, sizeof(s->icr));
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s->divide_conf = 0;
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s->count_shift = 0;
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s->initial_count = 0;
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s->initial_count_load_time = 0;
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s->next_time = 0;
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s->wait_for_sipi = !cpu_is_bsp(s->cpu);
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if (s->timer) {
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timer_del(s->timer);
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}
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s->timer_expiry = -1;
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info = APIC_COMMON_GET_CLASS(s);
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if (info->reset) {
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info->reset(s);
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}
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}
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void apic_designate_bsp(DeviceState *dev, bool bsp)
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{
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if (dev == NULL) {
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return;
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}
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APICCommonState *s = APIC_COMMON(dev);
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if (bsp) {
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s->apicbase |= MSR_IA32_APICBASE_BSP;
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} else {
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s->apicbase &= ~MSR_IA32_APICBASE_BSP;
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}
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}
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static void apic_reset_common(DeviceState *dev)
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{
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APICCommonState *s = APIC_COMMON(dev);
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APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
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uint32_t bsp;
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bsp = s->apicbase & MSR_IA32_APICBASE_BSP;
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s->apicbase = APIC_DEFAULT_ADDRESS | bsp | MSR_IA32_APICBASE_ENABLE;
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s->vapic_paddr = 0;
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info->vapic_base_update(s);
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apic_init_reset(dev);
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}
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/* This function is only used for old state version 1 and 2 */
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static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
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{
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APICCommonState *s = opaque;
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APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
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int i;
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if (version_id > 2) {
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return -EINVAL;
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}
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/* XXX: what if the base changes? (registered memory regions) */
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qemu_get_be32s(f, &s->apicbase);
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qemu_get_8s(f, &s->id);
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qemu_get_8s(f, &s->arb_id);
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qemu_get_8s(f, &s->tpr);
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qemu_get_be32s(f, &s->spurious_vec);
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qemu_get_8s(f, &s->log_dest);
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qemu_get_8s(f, &s->dest_mode);
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for (i = 0; i < 8; i++) {
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qemu_get_be32s(f, &s->isr[i]);
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qemu_get_be32s(f, &s->tmr[i]);
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qemu_get_be32s(f, &s->irr[i]);
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}
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for (i = 0; i < APIC_LVT_NB; i++) {
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qemu_get_be32s(f, &s->lvt[i]);
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}
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qemu_get_be32s(f, &s->esr);
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qemu_get_be32s(f, &s->icr[0]);
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qemu_get_be32s(f, &s->icr[1]);
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qemu_get_be32s(f, &s->divide_conf);
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s->count_shift = qemu_get_be32(f);
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qemu_get_be32s(f, &s->initial_count);
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s->initial_count_load_time = qemu_get_be64(f);
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s->next_time = qemu_get_be64(f);
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if (version_id >= 2) {
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s->timer_expiry = qemu_get_be64(f);
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}
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if (info->post_load) {
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info->post_load(s);
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}
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return 0;
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}
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static void apic_common_realize(DeviceState *dev, Error **errp)
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{
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APICCommonState *s = APIC_COMMON(dev);
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APICCommonClass *info;
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static DeviceState *vapic;
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static int apic_no;
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static bool mmio_registered;
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if (apic_no >= MAX_APICS) {
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error_setg(errp, "%s initialization failed.",
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object_get_typename(OBJECT(dev)));
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return;
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}
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s->idx = apic_no++;
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info = APIC_COMMON_GET_CLASS(s);
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info->realize(dev, errp);
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if (!mmio_registered) {
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ICCBus *b = ICC_BUS(qdev_get_parent_bus(dev));
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memory_region_add_subregion(b->apic_address_space, 0, &s->io_memory);
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mmio_registered = true;
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}
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/* Note: We need at least 1M to map the VAPIC option ROM */
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if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&
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ram_size >= 1024 * 1024) {
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vapic = sysbus_create_simple("kvmvapic", -1, NULL);
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}
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s->vapic = vapic;
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if (apic_report_tpr_access && info->enable_tpr_reporting) {
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info->enable_tpr_reporting(s, true);
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}
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}
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static int apic_pre_load(void *opaque)
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{
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APICCommonState *s = APIC_COMMON(opaque);
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/* The default is !cpu_is_bsp(s->cpu), but the common value is 0
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* so that's what apic_common_sipi_needed checks for. Reset to
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* the value that is assumed when the apic_sipi subsection is
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* absent.
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*/
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s->wait_for_sipi = 0;
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return 0;
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}
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static void apic_dispatch_pre_save(void *opaque)
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{
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APICCommonState *s = APIC_COMMON(opaque);
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APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
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if (info->pre_save) {
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info->pre_save(s);
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}
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}
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static int apic_dispatch_post_load(void *opaque, int version_id)
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{
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APICCommonState *s = APIC_COMMON(opaque);
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APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
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if (info->post_load) {
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info->post_load(s);
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}
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return 0;
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}
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static bool apic_common_sipi_needed(void *opaque)
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{
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APICCommonState *s = APIC_COMMON(opaque);
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return s->wait_for_sipi != 0;
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}
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static const VMStateDescription vmstate_apic_common_sipi = {
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.name = "apic_sipi",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = apic_common_sipi_needed,
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.fields = (VMStateField[]) {
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VMSTATE_INT32(sipi_vector, APICCommonState),
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VMSTATE_INT32(wait_for_sipi, APICCommonState),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_apic_common = {
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.name = "apic",
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.version_id = 3,
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.minimum_version_id = 3,
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.minimum_version_id_old = 1,
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.load_state_old = apic_load_old,
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.pre_load = apic_pre_load,
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.pre_save = apic_dispatch_pre_save,
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.post_load = apic_dispatch_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(apicbase, APICCommonState),
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VMSTATE_UINT8(id, APICCommonState),
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VMSTATE_UINT8(arb_id, APICCommonState),
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VMSTATE_UINT8(tpr, APICCommonState),
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VMSTATE_UINT32(spurious_vec, APICCommonState),
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VMSTATE_UINT8(log_dest, APICCommonState),
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VMSTATE_UINT8(dest_mode, APICCommonState),
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VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8),
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VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8),
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VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8),
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VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB),
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VMSTATE_UINT32(esr, APICCommonState),
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VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2),
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VMSTATE_UINT32(divide_conf, APICCommonState),
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VMSTATE_INT32(count_shift, APICCommonState),
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VMSTATE_UINT32(initial_count, APICCommonState),
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VMSTATE_INT64(initial_count_load_time, APICCommonState),
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VMSTATE_INT64(next_time, APICCommonState),
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VMSTATE_INT64(timer_expiry,
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APICCommonState), /* open-coded timer state */
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VMSTATE_END_OF_LIST()
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},
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.subsections = (const VMStateDescription*[]) {
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&vmstate_apic_common_sipi,
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NULL
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}
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};
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static Property apic_properties_common[] = {
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DEFINE_PROP_UINT8("id", APICCommonState, id, -1),
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DEFINE_PROP_UINT8("version", APICCommonState, version, 0x14),
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DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT,
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true),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void apic_common_class_init(ObjectClass *klass, void *data)
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{
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ICCDeviceClass *idc = ICC_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->vmsd = &vmstate_apic_common;
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dc->reset = apic_reset_common;
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dc->props = apic_properties_common;
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idc->realize = apic_common_realize;
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/*
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* Reason: APIC and CPU need to be wired up by
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* x86_cpu_apic_create()
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*/
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dc->cannot_instantiate_with_device_add_yet = true;
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}
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static const TypeInfo apic_common_type = {
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.name = TYPE_APIC_COMMON,
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.parent = TYPE_ICC_DEVICE,
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.instance_size = sizeof(APICCommonState),
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.class_size = sizeof(APICCommonClass),
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.class_init = apic_common_class_init,
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.abstract = true,
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};
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static void apic_common_register_types(void)
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{
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type_register_static(&apic_common_type);
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}
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type_init(apic_common_register_types)
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