7da845b0f4
Make the cache ID system registers (CLIDR, CSSELR, CCSIDR, CTR) visible to AArch64. These are mostly simple 64-bit extensions of the existing 32 bit system registers and so can share reginfo definitions. CTR needs to have a split definition, but we can clean up the temporary user-mode implementation in favour of using the CPU-specified reset value, and implement the system-mode-required semantics of restricting its EL0 accessibility if SCTLR.UCT is not set. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
134 lines
3.6 KiB
C
134 lines
3.6 KiB
C
/*
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* QEMU AArch64 CPU
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*
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* Copyright (c) 2013 Linaro Ltd
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see
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* <http://www.gnu.org/licenses/gpl-2.0.html>
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*/
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#include "cpu.h"
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#include "qemu-common.h"
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#if !defined(CONFIG_USER_ONLY)
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#include "hw/loader.h"
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#endif
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#include "hw/arm/arm.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/kvm.h"
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static inline void set_feature(CPUARMState *env, int feature)
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{
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env->features |= 1ULL << feature;
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}
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#ifdef CONFIG_USER_ONLY
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static void aarch64_any_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V8);
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set_feature(&cpu->env, ARM_FEATURE_VFP4);
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set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
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set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
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set_feature(&cpu->env, ARM_FEATURE_V7MP);
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set_feature(&cpu->env, ARM_FEATURE_AARCH64);
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cpu->ctr = 0x80030003; /* 32 byte I and D cacheline size, VIPT icache */
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}
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#endif
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typedef struct ARMCPUInfo {
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const char *name;
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void (*initfn)(Object *obj);
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void (*class_init)(ObjectClass *oc, void *data);
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} ARMCPUInfo;
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static const ARMCPUInfo aarch64_cpus[] = {
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#ifdef CONFIG_USER_ONLY
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{ .name = "any", .initfn = aarch64_any_initfn },
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#endif
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{ .name = NULL }
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};
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static void aarch64_cpu_initfn(Object *obj)
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{
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}
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static void aarch64_cpu_finalizefn(Object *obj)
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{
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}
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static void aarch64_cpu_set_pc(CPUState *cs, vaddr value)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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/*
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* TODO: this will need updating for system emulation,
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* when the core may be in AArch32 mode.
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*/
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cpu->env.pc = value;
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}
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static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
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{
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CPUClass *cc = CPU_CLASS(oc);
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cc->dump_state = aarch64_cpu_dump_state;
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cc->set_pc = aarch64_cpu_set_pc;
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cc->gdb_read_register = aarch64_cpu_gdb_read_register;
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cc->gdb_write_register = aarch64_cpu_gdb_write_register;
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cc->gdb_num_core_regs = 34;
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cc->gdb_core_xml_file = "aarch64-core.xml";
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}
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static void aarch64_cpu_register(const ARMCPUInfo *info)
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{
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TypeInfo type_info = {
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.parent = TYPE_AARCH64_CPU,
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.instance_size = sizeof(ARMCPU),
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.instance_init = info->initfn,
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.class_size = sizeof(ARMCPUClass),
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.class_init = info->class_init,
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};
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type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
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type_register(&type_info);
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g_free((void *)type_info.name);
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}
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static const TypeInfo aarch64_cpu_type_info = {
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.name = TYPE_AARCH64_CPU,
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.parent = TYPE_ARM_CPU,
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.instance_size = sizeof(ARMCPU),
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.instance_init = aarch64_cpu_initfn,
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.instance_finalize = aarch64_cpu_finalizefn,
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.abstract = true,
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.class_size = sizeof(AArch64CPUClass),
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.class_init = aarch64_cpu_class_init,
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};
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static void aarch64_cpu_register_types(void)
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{
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const ARMCPUInfo *info = aarch64_cpus;
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type_register_static(&aarch64_cpu_type_info);
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while (info->name) {
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aarch64_cpu_register(info);
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info++;
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}
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}
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type_init(aarch64_cpu_register_types)
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