471 lines
12 KiB
C
471 lines
12 KiB
C
/*
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* ColdFire Fast Ethernet Controller emulation.
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*
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* Copyright (c) 2007 CodeSourcery.
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*
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* This code is licenced under the GPL
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*/
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#include "hw.h"
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#include "net.h"
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#include "mcf.h"
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/* For crc32 */
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#include <zlib.h>
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//#define DEBUG_FEC 1
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#ifdef DEBUG_FEC
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#define DPRINTF(fmt, ...) \
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do { printf("mcf_fec: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...) do {} while(0)
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#endif
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#define FEC_MAX_FRAME_SIZE 2032
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typedef struct {
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qemu_irq *irq;
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int mmio_index;
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VLANClientState *vc;
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uint32_t irq_state;
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uint32_t eir;
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uint32_t eimr;
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int rx_enabled;
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uint32_t rx_descriptor;
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uint32_t tx_descriptor;
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uint32_t ecr;
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uint32_t mmfr;
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uint32_t mscr;
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uint32_t rcr;
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uint32_t tcr;
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uint32_t tfwr;
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uint32_t rfsr;
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uint32_t erdsr;
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uint32_t etdsr;
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uint32_t emrbr;
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uint8_t macaddr[6];
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} mcf_fec_state;
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#define FEC_INT_HB 0x80000000
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#define FEC_INT_BABR 0x40000000
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#define FEC_INT_BABT 0x20000000
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#define FEC_INT_GRA 0x10000000
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#define FEC_INT_TXF 0x08000000
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#define FEC_INT_TXB 0x04000000
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#define FEC_INT_RXF 0x02000000
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#define FEC_INT_RXB 0x01000000
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#define FEC_INT_MII 0x00800000
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#define FEC_INT_EB 0x00400000
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#define FEC_INT_LC 0x00200000
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#define FEC_INT_RL 0x00100000
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#define FEC_INT_UN 0x00080000
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#define FEC_EN 2
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#define FEC_RESET 1
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/* Map interrupt flags onto IRQ lines. */
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#define FEC_NUM_IRQ 13
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static const uint32_t mcf_fec_irq_map[FEC_NUM_IRQ] = {
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FEC_INT_TXF,
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FEC_INT_TXB,
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FEC_INT_UN,
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FEC_INT_RL,
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FEC_INT_RXF,
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FEC_INT_RXB,
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FEC_INT_MII,
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FEC_INT_LC,
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FEC_INT_HB,
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FEC_INT_GRA,
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FEC_INT_EB,
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FEC_INT_BABT,
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FEC_INT_BABR
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};
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/* Buffer Descriptor. */
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typedef struct {
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uint16_t flags;
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uint16_t length;
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uint32_t data;
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} mcf_fec_bd;
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#define FEC_BD_R 0x8000
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#define FEC_BD_E 0x8000
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#define FEC_BD_O1 0x4000
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#define FEC_BD_W 0x2000
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#define FEC_BD_O2 0x1000
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#define FEC_BD_L 0x0800
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#define FEC_BD_TC 0x0400
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#define FEC_BD_ABC 0x0200
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#define FEC_BD_M 0x0100
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#define FEC_BD_BC 0x0080
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#define FEC_BD_MC 0x0040
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#define FEC_BD_LG 0x0020
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#define FEC_BD_NO 0x0010
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#define FEC_BD_CR 0x0004
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#define FEC_BD_OV 0x0002
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#define FEC_BD_TR 0x0001
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static void mcf_fec_read_bd(mcf_fec_bd *bd, uint32_t addr)
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{
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cpu_physical_memory_read(addr, (uint8_t *)bd, sizeof(*bd));
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be16_to_cpus(&bd->flags);
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be16_to_cpus(&bd->length);
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be32_to_cpus(&bd->data);
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}
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static void mcf_fec_write_bd(mcf_fec_bd *bd, uint32_t addr)
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{
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mcf_fec_bd tmp;
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tmp.flags = cpu_to_be16(bd->flags);
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tmp.length = cpu_to_be16(bd->length);
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tmp.data = cpu_to_be32(bd->data);
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cpu_physical_memory_write(addr, (uint8_t *)&tmp, sizeof(tmp));
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}
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static void mcf_fec_update(mcf_fec_state *s)
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{
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uint32_t active;
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uint32_t changed;
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uint32_t mask;
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int i;
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active = s->eir & s->eimr;
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changed = active ^s->irq_state;
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for (i = 0; i < FEC_NUM_IRQ; i++) {
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mask = mcf_fec_irq_map[i];
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if (changed & mask) {
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DPRINTF("IRQ %d = %d\n", i, (active & mask) != 0);
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qemu_set_irq(s->irq[i], (active & mask) != 0);
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}
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}
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s->irq_state = active;
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}
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static void mcf_fec_do_tx(mcf_fec_state *s)
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{
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uint32_t addr;
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mcf_fec_bd bd;
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int frame_size;
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int len;
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uint8_t frame[FEC_MAX_FRAME_SIZE];
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uint8_t *ptr;
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DPRINTF("do_tx\n");
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ptr = frame;
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frame_size = 0;
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addr = s->tx_descriptor;
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while (1) {
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mcf_fec_read_bd(&bd, addr);
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DPRINTF("tx_bd %x flags %04x len %d data %08x\n",
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addr, bd.flags, bd.length, bd.data);
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if ((bd.flags & FEC_BD_R) == 0) {
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/* Run out of descriptors to transmit. */
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break;
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}
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len = bd.length;
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if (frame_size + len > FEC_MAX_FRAME_SIZE) {
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len = FEC_MAX_FRAME_SIZE - frame_size;
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s->eir |= FEC_INT_BABT;
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}
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cpu_physical_memory_read(bd.data, ptr, len);
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ptr += len;
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frame_size += len;
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if (bd.flags & FEC_BD_L) {
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/* Last buffer in frame. */
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DPRINTF("Sending packet\n");
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qemu_send_packet(s->vc, frame, len);
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ptr = frame;
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frame_size = 0;
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s->eir |= FEC_INT_TXF;
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}
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s->eir |= FEC_INT_TXB;
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bd.flags &= ~FEC_BD_R;
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/* Write back the modified descriptor. */
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mcf_fec_write_bd(&bd, addr);
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/* Advance to the next descriptor. */
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if ((bd.flags & FEC_BD_W) != 0) {
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addr = s->etdsr;
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} else {
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addr += 8;
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}
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}
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s->tx_descriptor = addr;
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}
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static void mcf_fec_enable_rx(mcf_fec_state *s)
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{
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mcf_fec_bd bd;
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mcf_fec_read_bd(&bd, s->rx_descriptor);
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s->rx_enabled = ((bd.flags & FEC_BD_E) != 0);
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if (!s->rx_enabled)
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DPRINTF("RX buffer full\n");
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}
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static void mcf_fec_reset(mcf_fec_state *s)
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{
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s->eir = 0;
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s->eimr = 0;
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s->rx_enabled = 0;
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s->ecr = 0;
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s->mscr = 0;
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s->rcr = 0x05ee0001;
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s->tcr = 0;
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s->tfwr = 0;
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s->rfsr = 0x500;
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}
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static uint32_t mcf_fec_read(void *opaque, target_phys_addr_t addr)
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{
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mcf_fec_state *s = (mcf_fec_state *)opaque;
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switch (addr & 0x3ff) {
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case 0x004: return s->eir;
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case 0x008: return s->eimr;
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case 0x010: return s->rx_enabled ? (1 << 24) : 0; /* RDAR */
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case 0x014: return 0; /* TDAR */
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case 0x024: return s->ecr;
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case 0x040: return s->mmfr;
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case 0x044: return s->mscr;
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case 0x064: return 0; /* MIBC */
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case 0x084: return s->rcr;
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case 0x0c4: return s->tcr;
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case 0x0e4: /* PALR */
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return (s->macaddr[0] << 24) | (s->macaddr[1] << 16)
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| (s->macaddr[2] << 8) | s->macaddr[3];
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break;
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case 0x0e8: /* PAUR */
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return (s->macaddr[4] << 24) | (s->macaddr[5] << 16) | 0x8808;
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case 0x0ec: return 0x10000; /* OPD */
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case 0x118: return 0;
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case 0x11c: return 0;
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case 0x120: return 0;
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case 0x124: return 0;
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case 0x144: return s->tfwr;
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case 0x14c: return 0x600;
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case 0x150: return s->rfsr;
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case 0x180: return s->erdsr;
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case 0x184: return s->etdsr;
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case 0x188: return s->emrbr;
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default:
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hw_error("mcf_fec_read: Bad address 0x%x\n", (int)addr);
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return 0;
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}
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}
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static void mcf_fec_write(void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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mcf_fec_state *s = (mcf_fec_state *)opaque;
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switch (addr & 0x3ff) {
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case 0x004:
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s->eir &= ~value;
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break;
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case 0x008:
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s->eimr = value;
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break;
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case 0x010: /* RDAR */
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if ((s->ecr & FEC_EN) && !s->rx_enabled) {
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DPRINTF("RX enable\n");
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mcf_fec_enable_rx(s);
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}
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break;
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case 0x014: /* TDAR */
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if (s->ecr & FEC_EN) {
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mcf_fec_do_tx(s);
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}
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break;
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case 0x024:
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s->ecr = value;
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if (value & FEC_RESET) {
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DPRINTF("Reset\n");
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mcf_fec_reset(s);
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}
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if ((s->ecr & FEC_EN) == 0) {
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s->rx_enabled = 0;
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}
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break;
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case 0x040:
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/* TODO: Implement MII. */
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s->mmfr = value;
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break;
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case 0x044:
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s->mscr = value & 0xfe;
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break;
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case 0x064:
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/* TODO: Implement MIB. */
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break;
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case 0x084:
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s->rcr = value & 0x07ff003f;
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/* TODO: Implement LOOP mode. */
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break;
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case 0x0c4: /* TCR */
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/* We transmit immediately, so raise GRA immediately. */
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s->tcr = value;
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if (value & 1)
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s->eir |= FEC_INT_GRA;
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break;
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case 0x0e4: /* PALR */
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s->macaddr[0] = value >> 24;
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s->macaddr[1] = value >> 16;
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s->macaddr[2] = value >> 8;
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s->macaddr[3] = value;
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break;
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case 0x0e8: /* PAUR */
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s->macaddr[4] = value >> 24;
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s->macaddr[5] = value >> 16;
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break;
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case 0x0ec:
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/* OPD */
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break;
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case 0x118:
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case 0x11c:
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case 0x120:
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case 0x124:
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/* TODO: implement MAC hash filtering. */
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break;
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case 0x144:
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s->tfwr = value & 3;
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break;
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case 0x14c:
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/* FRBR writes ignored. */
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break;
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case 0x150:
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s->rfsr = (value & 0x3fc) | 0x400;
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break;
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case 0x180:
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s->erdsr = value & ~3;
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s->rx_descriptor = s->erdsr;
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break;
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case 0x184:
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s->etdsr = value & ~3;
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s->tx_descriptor = s->etdsr;
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break;
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case 0x188:
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s->emrbr = value & 0x7f0;
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break;
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default:
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hw_error("mcf_fec_write Bad address 0x%x\n", (int)addr);
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}
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mcf_fec_update(s);
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}
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static int mcf_fec_can_receive(VLANClientState *vc)
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{
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mcf_fec_state *s = vc->opaque;
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return s->rx_enabled;
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}
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static ssize_t mcf_fec_receive(VLANClientState *vc, const uint8_t *buf, size_t size)
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{
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mcf_fec_state *s = vc->opaque;
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mcf_fec_bd bd;
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uint32_t flags = 0;
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uint32_t addr;
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uint32_t crc;
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uint32_t buf_addr;
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uint8_t *crc_ptr;
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unsigned int buf_len;
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DPRINTF("do_rx len %d\n", size);
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if (!s->rx_enabled) {
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fprintf(stderr, "mcf_fec_receive: Unexpected packet\n");
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}
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/* 4 bytes for the CRC. */
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size += 4;
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crc = cpu_to_be32(crc32(~0, buf, size));
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crc_ptr = (uint8_t *)&crc;
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/* Huge frames are truncted. */
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if (size > FEC_MAX_FRAME_SIZE) {
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size = FEC_MAX_FRAME_SIZE;
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flags |= FEC_BD_TR | FEC_BD_LG;
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}
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/* Frames larger than the user limit just set error flags. */
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if (size > (s->rcr >> 16)) {
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flags |= FEC_BD_LG;
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}
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addr = s->rx_descriptor;
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while (size > 0) {
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mcf_fec_read_bd(&bd, addr);
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if ((bd.flags & FEC_BD_E) == 0) {
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/* No descriptors available. Bail out. */
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/* FIXME: This is wrong. We should probably either save the
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remainder for when more RX buffers are available, or
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flag an error. */
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fprintf(stderr, "mcf_fec: Lost end of frame\n");
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break;
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}
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buf_len = (size <= s->emrbr) ? size: s->emrbr;
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bd.length = buf_len;
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size -= buf_len;
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DPRINTF("rx_bd %x length %d\n", addr, bd.length);
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/* The last 4 bytes are the CRC. */
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if (size < 4)
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buf_len += size - 4;
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buf_addr = bd.data;
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cpu_physical_memory_write(buf_addr, buf, buf_len);
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buf += buf_len;
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if (size < 4) {
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cpu_physical_memory_write(buf_addr + buf_len, crc_ptr, 4 - size);
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crc_ptr += 4 - size;
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}
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bd.flags &= ~FEC_BD_E;
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if (size == 0) {
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/* Last buffer in frame. */
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bd.flags |= flags | FEC_BD_L;
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DPRINTF("rx frame flags %04x\n", bd.flags);
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s->eir |= FEC_INT_RXF;
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} else {
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s->eir |= FEC_INT_RXB;
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}
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mcf_fec_write_bd(&bd, addr);
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/* Advance to the next descriptor. */
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if ((bd.flags & FEC_BD_W) != 0) {
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addr = s->erdsr;
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} else {
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addr += 8;
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}
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}
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s->rx_descriptor = addr;
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mcf_fec_enable_rx(s);
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mcf_fec_update(s);
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return size;
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}
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static CPUReadMemoryFunc * const mcf_fec_readfn[] = {
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mcf_fec_read,
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mcf_fec_read,
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mcf_fec_read
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};
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static CPUWriteMemoryFunc * const mcf_fec_writefn[] = {
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mcf_fec_write,
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mcf_fec_write,
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mcf_fec_write
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};
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static void mcf_fec_cleanup(VLANClientState *vc)
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{
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mcf_fec_state *s = vc->opaque;
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cpu_unregister_io_memory(s->mmio_index);
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qemu_free(s);
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}
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void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq)
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{
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mcf_fec_state *s;
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qemu_check_nic_model(nd, "mcf_fec");
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s = (mcf_fec_state *)qemu_mallocz(sizeof(mcf_fec_state));
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s->irq = irq;
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s->mmio_index = cpu_register_io_memory(mcf_fec_readfn,
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mcf_fec_writefn, s);
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cpu_register_physical_memory(base, 0x400, s->mmio_index);
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s->vc = nd->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name,
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mcf_fec_can_receive, mcf_fec_receive,
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NULL, mcf_fec_cleanup, s);
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memcpy(s->macaddr, nd->macaddr, 6);
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qemu_format_nic_info_str(s->vc, s->macaddr);
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}
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