qemu/target-i386
Martin Simmons 8001c294f8 target-i386: Make x86 mfence and lfence illegal without SSE2
While trying to use qemu -cpu pentium3 to test for incorrect uses of certain
SSE2 instructions, I found that QEMU allowed the mfence and lfence
instructions to be executed even though Pentium 3 doesn't support them.

According to the processor specs (and experience on a real Pentium 3), these
instructions are only available with SSE2, but QEMU is checking for SSE.  The
check for the related sfence instruction is correct (it works with SSE).

This trival patch fixes the test.

Signed-off-by: Martin Simmons <martin@lispworks.com>
Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-06-08 09:04:29 +01:00
..
cpu.h target-i386: remove old code handling float64 2011-06-03 16:07:50 +02:00
cpuid.c kvm: add kvmclock to its second bit 2011-05-02 09:38:35 -03:00
exec.h target-i386: remove old code handling float64 2011-06-03 16:07:50 +02:00
helper_template.h
helper.c Fix compilation warning due to missing header for sigaction (followup) 2011-06-08 09:04:29 +01:00
helper.h
kvm.c kvm: use qemu_free consistently 2011-05-02 09:51:59 -03:00
machine.c target-i386: remove old code handling float64 2011-06-03 16:07:50 +02:00
op_helper.c target-i386: use floatx80 constants in helper_fld*_ST0() 2011-06-03 16:07:52 +02:00
ops_sse_header.h tcg: Optionally sign-extend 32-bit arguments for 64-bit hosts. 2010-06-16 11:29:11 +02:00
ops_sse.h target-i386: replace approx_rsqrt and approx_rcp by softfloat ops 2011-04-25 11:18:33 +02:00
svm.h
TODO
translate.c target-i386: Make x86 mfence and lfence illegal without SSE2 2011-06-08 09:04:29 +01:00