7ff7ea9280
The XiveRouter models the second sub-engine of the XIVE architecture : the Interrupt Virtualization Routing Engine (IVRE). The IVRE handles event notifications of the IVSE and performs the interrupt routing process. For this purpose, it uses a set of tables stored in system memory, the first of which being the Event Assignment Structure (EAS) table. The EAT associates an interrupt source number with an Event Notification Descriptor (END) which will be used in a second phase of the routing process to identify a Notification Virtual Target. The XiveRouter is an abstract class which needs to be inherited from to define a storage for the EAT, and other upcoming tables. Signed-off-by: Cédric Le Goater <clg@kaod.org> [dwg: Folded in parts of a later fix by Cédric fixing field access] [dwg: Fix style nits] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
63 lines
1.9 KiB
C
63 lines
1.9 KiB
C
/*
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* QEMU PowerPC XIVE internal structure definitions
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*
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*
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* The XIVE structures are accessed by the HW and their format is
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* architected to be big-endian. Some macros are provided to ease
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* access to the different fields.
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*
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*
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* Copyright (c) 2016-2018, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#ifndef PPC_XIVE_REGS_H
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#define PPC_XIVE_REGS_H
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/*
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* Interrupt source number encoding on PowerBUS
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*/
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#define XIVE_SRCNO_BLOCK(srcno) (((srcno) >> 28) & 0xf)
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#define XIVE_SRCNO_INDEX(srcno) ((srcno) & 0x0fffffff)
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#define XIVE_SRCNO(blk, idx) ((uint32_t)(blk) << 28 | (idx))
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/*
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* EAS (Event Assignment Structure)
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*
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* One per interrupt source. Targets an interrupt to a given Event
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* Notification Descriptor (END) and provides the corresponding
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* logical interrupt number (END data)
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*/
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typedef struct XiveEAS {
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/*
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* Use a single 64-bit definition to make it easier to perform
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* atomic updates
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*/
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uint64_t w;
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#define EAS_VALID PPC_BIT(0)
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#define EAS_END_BLOCK PPC_BITMASK(4, 7) /* Destination END block# */
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#define EAS_END_INDEX PPC_BITMASK(8, 31) /* Destination END index */
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#define EAS_MASKED PPC_BIT(32) /* Masked */
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#define EAS_END_DATA PPC_BITMASK(33, 63) /* Data written to the END */
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} XiveEAS;
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#define xive_eas_is_valid(eas) (be64_to_cpu((eas)->w) & EAS_VALID)
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#define xive_eas_is_masked(eas) (be64_to_cpu((eas)->w) & EAS_MASKED)
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static inline uint64_t xive_get_field64(uint64_t mask, uint64_t word)
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{
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return (be64_to_cpu(word) & mask) >> ctz64(mask);
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}
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static inline uint64_t xive_set_field64(uint64_t mask, uint64_t word,
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uint64_t value)
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{
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uint64_t tmp =
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(be64_to_cpu(word) & ~mask) | ((value << ctz64(mask)) & mask);
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return cpu_to_be64(tmp);
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}
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#endif /* PPC_XIVE_REGS_H */
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