dd7b952b79
Xtensa cores may have registers of types/sizes not supported by the gdbstub accessors. Ignore writes to such registers and return zero on read, but always return correct register size, so that gdb on the other side is able to access all registers in the packet holding unsupported registers in the middle. This fixes gdb interaction with cores that have vector/custom TIE registers. Cc: qemu-stable@nongnu.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
136 lines
3.9 KiB
C
136 lines
3.9 KiB
C
/*
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* Xtensa gdb server stub
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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* Copyright (c) 2013 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "exec/gdbstub.h"
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#include "qemu/log.h"
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int xtensa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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XtensaCPU *cpu = XTENSA_CPU(cs);
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CPUXtensaState *env = &cpu->env;
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const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
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unsigned i;
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if (n < 0 || n >= env->config->gdb_regmap.num_regs) {
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return 0;
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}
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switch (reg->type) {
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case 9: /*pc*/
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return gdb_get_reg32(mem_buf, env->pc);
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case 1: /*ar*/
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xtensa_sync_phys_from_window(env);
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return gdb_get_reg32(mem_buf, env->phys_regs[(reg->targno & 0xff)
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% env->config->nareg]);
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case 2: /*SR*/
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return gdb_get_reg32(mem_buf, env->sregs[reg->targno & 0xff]);
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case 3: /*UR*/
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return gdb_get_reg32(mem_buf, env->uregs[reg->targno & 0xff]);
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case 4: /*f*/
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i = reg->targno & 0x0f;
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switch (reg->size) {
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case 4:
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return gdb_get_reg32(mem_buf,
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float32_val(env->fregs[i].f32[FP_F32_LOW]));
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case 8:
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return gdb_get_reg64(mem_buf, float64_val(env->fregs[i].f64));
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default:
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qemu_log_mask(LOG_UNIMP, "%s from reg %d of unsupported size %d\n",
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__func__, n, reg->size);
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memset(mem_buf, 0, reg->size);
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return reg->size;
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}
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case 8: /*a*/
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return gdb_get_reg32(mem_buf, env->regs[reg->targno & 0x0f]);
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default:
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qemu_log_mask(LOG_UNIMP, "%s from reg %d of unsupported type %d\n",
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__func__, n, reg->type);
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memset(mem_buf, 0, reg->size);
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return reg->size;
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return 0;
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}
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}
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int xtensa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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XtensaCPU *cpu = XTENSA_CPU(cs);
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CPUXtensaState *env = &cpu->env;
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uint32_t tmp;
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const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
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if (n < 0 || n >= env->config->gdb_regmap.num_regs) {
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return 0;
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}
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tmp = ldl_p(mem_buf);
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switch (reg->type) {
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case 9: /*pc*/
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env->pc = tmp;
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break;
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case 1: /*ar*/
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env->phys_regs[(reg->targno & 0xff) % env->config->nareg] = tmp;
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xtensa_sync_window_from_phys(env);
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break;
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case 2: /*SR*/
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env->sregs[reg->targno & 0xff] = tmp;
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break;
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case 3: /*UR*/
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env->uregs[reg->targno & 0xff] = tmp;
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break;
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case 4: /*f*/
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switch (reg->size) {
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case 4:
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env->fregs[reg->targno & 0x0f].f32[FP_F32_LOW] = make_float32(tmp);
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return 4;
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case 8:
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env->fregs[reg->targno & 0x0f].f64 = make_float64(tmp);
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return 8;
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default:
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qemu_log_mask(LOG_UNIMP, "%s to reg %d of unsupported size %d\n",
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__func__, n, reg->size);
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return reg->size;
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}
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case 8: /*a*/
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env->regs[reg->targno & 0x0f] = tmp;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "%s to reg %d of unsupported type %d\n",
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__func__, n, reg->type);
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return reg->size;
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}
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return 4;
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}
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