12ec8bd51e
The header file hw/arm/arm.h now includes only declarations relating to hw/arm/boot.c functionality. Rename it accordingly, and adjust its header comment. The bulk of this commit was created via perl -pi -e 's|hw/arm/arm.h|hw/arm/boot.h|' hw/arm/*.c include/hw/arm/*.h In a few cases we can just delete the #include: hw/arm/msf2-soc.c, include/hw/arm/aspeed_soc.h and include/hw/arm/bcm2836.h did not require it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190516163857.6430-4-peter.maydell@linaro.org
730 lines
21 KiB
C
730 lines
21 KiB
C
/*
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* ARM Integrator CP System emulation.
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*
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* Copyright (c) 2005-2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GPL
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "hw/sysbus.h"
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#include "hw/boards.h"
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#include "hw/arm/boot.h"
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#include "hw/misc/arm_integrator_debug.h"
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#include "hw/net/smc91c111.h"
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#include "net/net.h"
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#include "exec/address-spaces.h"
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#include "sysemu/sysemu.h"
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#include "qemu/error-report.h"
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#include "hw/char/pl011.h"
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#define TYPE_INTEGRATOR_CM "integrator_core"
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#define INTEGRATOR_CM(obj) \
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OBJECT_CHECK(IntegratorCMState, (obj), TYPE_INTEGRATOR_CM)
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typedef struct IntegratorCMState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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uint32_t memsz;
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MemoryRegion flash;
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uint32_t cm_osc;
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uint32_t cm_ctrl;
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uint32_t cm_lock;
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uint32_t cm_auxosc;
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uint32_t cm_sdram;
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uint32_t cm_init;
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uint32_t cm_flags;
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uint32_t cm_nvflags;
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uint32_t cm_refcnt_offset;
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uint32_t int_level;
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uint32_t irq_enabled;
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uint32_t fiq_enabled;
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} IntegratorCMState;
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static uint8_t integrator_spd[128] = {
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128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
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0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
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};
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static const VMStateDescription vmstate_integratorcm = {
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.name = "integratorcm",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(cm_osc, IntegratorCMState),
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VMSTATE_UINT32(cm_ctrl, IntegratorCMState),
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VMSTATE_UINT32(cm_lock, IntegratorCMState),
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VMSTATE_UINT32(cm_auxosc, IntegratorCMState),
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VMSTATE_UINT32(cm_sdram, IntegratorCMState),
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VMSTATE_UINT32(cm_init, IntegratorCMState),
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VMSTATE_UINT32(cm_flags, IntegratorCMState),
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VMSTATE_UINT32(cm_nvflags, IntegratorCMState),
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VMSTATE_UINT32(int_level, IntegratorCMState),
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VMSTATE_UINT32(irq_enabled, IntegratorCMState),
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VMSTATE_UINT32(fiq_enabled, IntegratorCMState),
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VMSTATE_END_OF_LIST()
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}
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};
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static uint64_t integratorcm_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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IntegratorCMState *s = opaque;
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if (offset >= 0x100 && offset < 0x200) {
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/* CM_SPD */
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if (offset >= 0x180)
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return 0;
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return integrator_spd[offset >> 2];
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}
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switch (offset >> 2) {
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case 0: /* CM_ID */
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return 0x411a3001;
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case 1: /* CM_PROC */
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return 0;
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case 2: /* CM_OSC */
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return s->cm_osc;
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case 3: /* CM_CTRL */
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return s->cm_ctrl;
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case 4: /* CM_STAT */
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return 0x00100000;
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case 5: /* CM_LOCK */
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if (s->cm_lock == 0xa05f) {
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return 0x1a05f;
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} else {
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return s->cm_lock;
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}
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case 6: /* CM_LMBUSCNT */
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/* ??? High frequency timer. */
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hw_error("integratorcm_read: CM_LMBUSCNT");
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case 7: /* CM_AUXOSC */
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return s->cm_auxosc;
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case 8: /* CM_SDRAM */
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return s->cm_sdram;
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case 9: /* CM_INIT */
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return s->cm_init;
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case 10: /* CM_REFCNT */
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/* This register, CM_REFCNT, provides a 32-bit count value.
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* The count increments at the fixed reference clock frequency of 24MHz
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* and can be used as a real-time counter.
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*/
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return (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24,
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1000) - s->cm_refcnt_offset;
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case 12: /* CM_FLAGS */
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return s->cm_flags;
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case 14: /* CM_NVFLAGS */
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return s->cm_nvflags;
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case 16: /* CM_IRQ_STAT */
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return s->int_level & s->irq_enabled;
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case 17: /* CM_IRQ_RSTAT */
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return s->int_level;
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case 18: /* CM_IRQ_ENSET */
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return s->irq_enabled;
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case 20: /* CM_SOFT_INTSET */
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return s->int_level & 1;
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case 24: /* CM_FIQ_STAT */
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return s->int_level & s->fiq_enabled;
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case 25: /* CM_FIQ_RSTAT */
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return s->int_level;
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case 26: /* CM_FIQ_ENSET */
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return s->fiq_enabled;
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case 32: /* CM_VOLTAGE_CTL0 */
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case 33: /* CM_VOLTAGE_CTL1 */
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case 34: /* CM_VOLTAGE_CTL2 */
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case 35: /* CM_VOLTAGE_CTL3 */
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/* ??? Voltage control unimplemented. */
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return 0;
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default:
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hw_error("integratorcm_read: Unimplemented offset 0x%x\n",
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(int)offset);
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return 0;
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}
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}
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static void integratorcm_do_remap(IntegratorCMState *s)
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{
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/* Sync memory region state with CM_CTRL REMAP bit:
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* bit 0 => flash at address 0; bit 1 => RAM
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*/
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memory_region_set_enabled(&s->flash, !(s->cm_ctrl & 4));
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}
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static void integratorcm_set_ctrl(IntegratorCMState *s, uint32_t value)
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{
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if (value & 8) {
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qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
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}
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if ((s->cm_ctrl ^ value) & 1) {
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/* (value & 1) != 0 means the green "MISC LED" is lit.
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* We don't have any nice place to display LEDs. printf is a bad
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* idea because Linux uses the LED as a heartbeat and the output
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* will swamp anything else on the terminal.
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*/
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}
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/* Note that the RESET bit [3] always reads as zero */
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s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5);
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integratorcm_do_remap(s);
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}
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static void integratorcm_update(IntegratorCMState *s)
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{
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/* ??? The CPU irq/fiq is raised when either the core module or base PIC
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are active. */
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if (s->int_level & (s->irq_enabled | s->fiq_enabled))
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hw_error("Core module interrupt\n");
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}
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static void integratorcm_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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IntegratorCMState *s = opaque;
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switch (offset >> 2) {
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case 2: /* CM_OSC */
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if (s->cm_lock == 0xa05f)
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s->cm_osc = value;
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break;
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case 3: /* CM_CTRL */
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integratorcm_set_ctrl(s, value);
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break;
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case 5: /* CM_LOCK */
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s->cm_lock = value & 0xffff;
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break;
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case 7: /* CM_AUXOSC */
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if (s->cm_lock == 0xa05f)
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s->cm_auxosc = value;
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break;
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case 8: /* CM_SDRAM */
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s->cm_sdram = value;
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break;
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case 9: /* CM_INIT */
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/* ??? This can change the memory bus frequency. */
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s->cm_init = value;
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break;
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case 12: /* CM_FLAGSS */
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s->cm_flags |= value;
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break;
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case 13: /* CM_FLAGSC */
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s->cm_flags &= ~value;
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break;
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case 14: /* CM_NVFLAGSS */
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s->cm_nvflags |= value;
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break;
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case 15: /* CM_NVFLAGSS */
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s->cm_nvflags &= ~value;
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break;
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case 18: /* CM_IRQ_ENSET */
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s->irq_enabled |= value;
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integratorcm_update(s);
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break;
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case 19: /* CM_IRQ_ENCLR */
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s->irq_enabled &= ~value;
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integratorcm_update(s);
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break;
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case 20: /* CM_SOFT_INTSET */
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s->int_level |= (value & 1);
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integratorcm_update(s);
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break;
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case 21: /* CM_SOFT_INTCLR */
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s->int_level &= ~(value & 1);
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integratorcm_update(s);
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break;
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case 26: /* CM_FIQ_ENSET */
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s->fiq_enabled |= value;
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integratorcm_update(s);
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break;
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case 27: /* CM_FIQ_ENCLR */
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s->fiq_enabled &= ~value;
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integratorcm_update(s);
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break;
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case 32: /* CM_VOLTAGE_CTL0 */
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case 33: /* CM_VOLTAGE_CTL1 */
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case 34: /* CM_VOLTAGE_CTL2 */
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case 35: /* CM_VOLTAGE_CTL3 */
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/* ??? Voltage control unimplemented. */
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break;
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default:
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hw_error("integratorcm_write: Unimplemented offset 0x%x\n",
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(int)offset);
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break;
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}
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}
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/* Integrator/CM control registers. */
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static const MemoryRegionOps integratorcm_ops = {
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.read = integratorcm_read,
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.write = integratorcm_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void integratorcm_init(Object *obj)
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{
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IntegratorCMState *s = INTEGRATOR_CM(obj);
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s->cm_osc = 0x01000048;
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/* ??? What should the high bits of this value be? */
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s->cm_auxosc = 0x0007feff;
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s->cm_sdram = 0x00011122;
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memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
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s->cm_init = 0x00000112;
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s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24,
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1000);
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/* ??? Save/restore. */
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}
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static void integratorcm_realize(DeviceState *d, Error **errp)
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{
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IntegratorCMState *s = INTEGRATOR_CM(d);
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SysBusDevice *dev = SYS_BUS_DEVICE(d);
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Error *local_err = NULL;
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memory_region_init_ram(&s->flash, OBJECT(d), "integrator.flash", 0x100000,
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&local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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memory_region_init_io(&s->iomem, OBJECT(d), &integratorcm_ops, s,
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"integratorcm", 0x00800000);
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sysbus_init_mmio(dev, &s->iomem);
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integratorcm_do_remap(s);
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if (s->memsz >= 256) {
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integrator_spd[31] = 64;
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s->cm_sdram |= 0x10;
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} else if (s->memsz >= 128) {
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integrator_spd[31] = 32;
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s->cm_sdram |= 0x0c;
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} else if (s->memsz >= 64) {
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integrator_spd[31] = 16;
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s->cm_sdram |= 0x08;
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} else if (s->memsz >= 32) {
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integrator_spd[31] = 4;
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s->cm_sdram |= 0x04;
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} else {
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integrator_spd[31] = 2;
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}
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}
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/* Integrator/CP hardware emulation. */
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/* Primary interrupt controller. */
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#define TYPE_INTEGRATOR_PIC "integrator_pic"
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#define INTEGRATOR_PIC(obj) \
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OBJECT_CHECK(icp_pic_state, (obj), TYPE_INTEGRATOR_PIC)
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typedef struct icp_pic_state {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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uint32_t level;
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uint32_t irq_enabled;
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uint32_t fiq_enabled;
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qemu_irq parent_irq;
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qemu_irq parent_fiq;
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} icp_pic_state;
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static const VMStateDescription vmstate_icp_pic = {
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.name = "icp_pic",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(level, icp_pic_state),
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VMSTATE_UINT32(irq_enabled, icp_pic_state),
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VMSTATE_UINT32(fiq_enabled, icp_pic_state),
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VMSTATE_END_OF_LIST()
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}
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};
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static void icp_pic_update(icp_pic_state *s)
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{
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uint32_t flags;
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flags = (s->level & s->irq_enabled);
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qemu_set_irq(s->parent_irq, flags != 0);
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flags = (s->level & s->fiq_enabled);
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qemu_set_irq(s->parent_fiq, flags != 0);
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}
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static void icp_pic_set_irq(void *opaque, int irq, int level)
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{
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icp_pic_state *s = (icp_pic_state *)opaque;
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if (level)
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s->level |= 1 << irq;
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else
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s->level &= ~(1 << irq);
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icp_pic_update(s);
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}
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static uint64_t icp_pic_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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icp_pic_state *s = (icp_pic_state *)opaque;
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switch (offset >> 2) {
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case 0: /* IRQ_STATUS */
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return s->level & s->irq_enabled;
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case 1: /* IRQ_RAWSTAT */
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return s->level;
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case 2: /* IRQ_ENABLESET */
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return s->irq_enabled;
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case 4: /* INT_SOFTSET */
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return s->level & 1;
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case 8: /* FRQ_STATUS */
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return s->level & s->fiq_enabled;
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case 9: /* FRQ_RAWSTAT */
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return s->level;
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case 10: /* FRQ_ENABLESET */
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return s->fiq_enabled;
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case 3: /* IRQ_ENABLECLR */
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case 5: /* INT_SOFTCLR */
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case 11: /* FRQ_ENABLECLR */
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default:
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printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset);
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return 0;
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}
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}
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static void icp_pic_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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icp_pic_state *s = (icp_pic_state *)opaque;
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switch (offset >> 2) {
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case 2: /* IRQ_ENABLESET */
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s->irq_enabled |= value;
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break;
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case 3: /* IRQ_ENABLECLR */
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s->irq_enabled &= ~value;
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break;
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case 4: /* INT_SOFTSET */
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if (value & 1)
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icp_pic_set_irq(s, 0, 1);
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break;
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case 5: /* INT_SOFTCLR */
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if (value & 1)
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icp_pic_set_irq(s, 0, 0);
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break;
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case 10: /* FRQ_ENABLESET */
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s->fiq_enabled |= value;
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break;
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case 11: /* FRQ_ENABLECLR */
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s->fiq_enabled &= ~value;
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break;
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case 0: /* IRQ_STATUS */
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case 1: /* IRQ_RAWSTAT */
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case 8: /* FRQ_STATUS */
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case 9: /* FRQ_RAWSTAT */
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default:
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printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset);
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return;
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}
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icp_pic_update(s);
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}
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static const MemoryRegionOps icp_pic_ops = {
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.read = icp_pic_read,
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.write = icp_pic_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void icp_pic_init(Object *obj)
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{
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DeviceState *dev = DEVICE(obj);
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icp_pic_state *s = INTEGRATOR_PIC(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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qdev_init_gpio_in(dev, icp_pic_set_irq, 32);
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sysbus_init_irq(sbd, &s->parent_irq);
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sysbus_init_irq(sbd, &s->parent_fiq);
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memory_region_init_io(&s->iomem, obj, &icp_pic_ops, s,
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"icp-pic", 0x00800000);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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/* CP control registers. */
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#define TYPE_ICP_CONTROL_REGS "icp-ctrl-regs"
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#define ICP_CONTROL_REGS(obj) \
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OBJECT_CHECK(ICPCtrlRegsState, (obj), TYPE_ICP_CONTROL_REGS)
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typedef struct ICPCtrlRegsState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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qemu_irq mmc_irq;
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uint32_t intreg_state;
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} ICPCtrlRegsState;
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#define ICP_GPIO_MMC_WPROT "mmc-wprot"
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#define ICP_GPIO_MMC_CARDIN "mmc-cardin"
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#define ICP_INTREG_WPROT (1 << 0)
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#define ICP_INTREG_CARDIN (1 << 3)
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static const VMStateDescription vmstate_icp_control = {
|
|
.name = "icp_control",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT32(intreg_state, ICPCtrlRegsState),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static uint64_t icp_control_read(void *opaque, hwaddr offset,
|
|
unsigned size)
|
|
{
|
|
ICPCtrlRegsState *s = opaque;
|
|
|
|
switch (offset >> 2) {
|
|
case 0: /* CP_IDFIELD */
|
|
return 0x41034003;
|
|
case 1: /* CP_FLASHPROG */
|
|
return 0;
|
|
case 2: /* CP_INTREG */
|
|
return s->intreg_state;
|
|
case 3: /* CP_DECODE */
|
|
return 0x11;
|
|
default:
|
|
hw_error("icp_control_read: Bad offset %x\n", (int)offset);
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
static void icp_control_write(void *opaque, hwaddr offset,
|
|
uint64_t value, unsigned size)
|
|
{
|
|
ICPCtrlRegsState *s = opaque;
|
|
|
|
switch (offset >> 2) {
|
|
case 2: /* CP_INTREG */
|
|
s->intreg_state &= ~(value & ICP_INTREG_CARDIN);
|
|
qemu_set_irq(s->mmc_irq, !!(s->intreg_state & ICP_INTREG_CARDIN));
|
|
break;
|
|
case 1: /* CP_FLASHPROG */
|
|
case 3: /* CP_DECODE */
|
|
/* Nothing interesting implemented yet. */
|
|
break;
|
|
default:
|
|
hw_error("icp_control_write: Bad offset %x\n", (int)offset);
|
|
}
|
|
}
|
|
|
|
static const MemoryRegionOps icp_control_ops = {
|
|
.read = icp_control_read,
|
|
.write = icp_control_write,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
};
|
|
|
|
static void icp_control_mmc_wprot(void *opaque, int line, int level)
|
|
{
|
|
ICPCtrlRegsState *s = opaque;
|
|
|
|
s->intreg_state &= ~ICP_INTREG_WPROT;
|
|
if (level) {
|
|
s->intreg_state |= ICP_INTREG_WPROT;
|
|
}
|
|
}
|
|
|
|
static void icp_control_mmc_cardin(void *opaque, int line, int level)
|
|
{
|
|
ICPCtrlRegsState *s = opaque;
|
|
|
|
/* line is released by writing to CP_INTREG */
|
|
if (level) {
|
|
s->intreg_state |= ICP_INTREG_CARDIN;
|
|
qemu_set_irq(s->mmc_irq, 1);
|
|
}
|
|
}
|
|
|
|
static void icp_control_init(Object *obj)
|
|
{
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
|
ICPCtrlRegsState *s = ICP_CONTROL_REGS(obj);
|
|
DeviceState *dev = DEVICE(obj);
|
|
|
|
memory_region_init_io(&s->iomem, OBJECT(s), &icp_control_ops, s,
|
|
"icp_ctrl_regs", 0x00800000);
|
|
sysbus_init_mmio(sbd, &s->iomem);
|
|
|
|
qdev_init_gpio_in_named(dev, icp_control_mmc_wprot, ICP_GPIO_MMC_WPROT, 1);
|
|
qdev_init_gpio_in_named(dev, icp_control_mmc_cardin,
|
|
ICP_GPIO_MMC_CARDIN, 1);
|
|
sysbus_init_irq(sbd, &s->mmc_irq);
|
|
}
|
|
|
|
|
|
/* Board init. */
|
|
|
|
static struct arm_boot_info integrator_binfo = {
|
|
.loader_start = 0x0,
|
|
.board_id = 0x113,
|
|
};
|
|
|
|
static void integratorcp_init(MachineState *machine)
|
|
{
|
|
ram_addr_t ram_size = machine->ram_size;
|
|
const char *kernel_filename = machine->kernel_filename;
|
|
const char *kernel_cmdline = machine->kernel_cmdline;
|
|
const char *initrd_filename = machine->initrd_filename;
|
|
Object *cpuobj;
|
|
ARMCPU *cpu;
|
|
MemoryRegion *address_space_mem = get_system_memory();
|
|
MemoryRegion *ram = g_new(MemoryRegion, 1);
|
|
MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
|
|
qemu_irq pic[32];
|
|
DeviceState *dev, *sic, *icp;
|
|
int i;
|
|
|
|
cpuobj = object_new(machine->cpu_type);
|
|
|
|
/* By default ARM1176 CPUs have EL3 enabled. This board does not
|
|
* currently support EL3 so the CPU EL3 property is disabled before
|
|
* realization.
|
|
*/
|
|
if (object_property_find(cpuobj, "has_el3", NULL)) {
|
|
object_property_set_bool(cpuobj, false, "has_el3", &error_fatal);
|
|
}
|
|
|
|
object_property_set_bool(cpuobj, true, "realized", &error_fatal);
|
|
|
|
cpu = ARM_CPU(cpuobj);
|
|
|
|
memory_region_allocate_system_memory(ram, NULL, "integrator.ram",
|
|
ram_size);
|
|
/* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */
|
|
/* ??? RAM should repeat to fill physical memory space. */
|
|
/* SDRAM at address zero*/
|
|
memory_region_add_subregion(address_space_mem, 0, ram);
|
|
/* And again at address 0x80000000 */
|
|
memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size);
|
|
memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias);
|
|
|
|
dev = qdev_create(NULL, TYPE_INTEGRATOR_CM);
|
|
qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
|
|
qdev_init_nofail(dev);
|
|
sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000);
|
|
|
|
dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000,
|
|
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ),
|
|
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ),
|
|
NULL);
|
|
for (i = 0; i < 32; i++) {
|
|
pic[i] = qdev_get_gpio_in(dev, i);
|
|
}
|
|
sic = sysbus_create_simple(TYPE_INTEGRATOR_PIC, 0xca000000, pic[26]);
|
|
sysbus_create_varargs("integrator_pit", 0x13000000,
|
|
pic[5], pic[6], pic[7], NULL);
|
|
sysbus_create_simple("pl031", 0x15000000, pic[8]);
|
|
pl011_create(0x16000000, pic[1], serial_hd(0));
|
|
pl011_create(0x17000000, pic[2], serial_hd(1));
|
|
icp = sysbus_create_simple(TYPE_ICP_CONTROL_REGS, 0xcb000000,
|
|
qdev_get_gpio_in(sic, 3));
|
|
sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]);
|
|
sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]);
|
|
sysbus_create_simple(TYPE_INTEGRATOR_DEBUG, 0x1a000000, 0);
|
|
|
|
dev = sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL);
|
|
qdev_connect_gpio_out(dev, 0,
|
|
qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0));
|
|
qdev_connect_gpio_out(dev, 1,
|
|
qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0));
|
|
|
|
if (nd_table[0].used)
|
|
smc91c111_init(&nd_table[0], 0xc8000000, pic[27]);
|
|
|
|
sysbus_create_simple("pl110", 0xc0000000, pic[22]);
|
|
|
|
integrator_binfo.ram_size = ram_size;
|
|
integrator_binfo.kernel_filename = kernel_filename;
|
|
integrator_binfo.kernel_cmdline = kernel_cmdline;
|
|
integrator_binfo.initrd_filename = initrd_filename;
|
|
arm_load_kernel(cpu, &integrator_binfo);
|
|
}
|
|
|
|
static void integratorcp_machine_init(MachineClass *mc)
|
|
{
|
|
mc->desc = "ARM Integrator/CP (ARM926EJ-S)";
|
|
mc->init = integratorcp_init;
|
|
mc->ignore_memory_transaction_failures = true;
|
|
mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
|
|
}
|
|
|
|
DEFINE_MACHINE("integratorcp", integratorcp_machine_init)
|
|
|
|
static Property core_properties[] = {
|
|
DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void core_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->props = core_properties;
|
|
dc->realize = integratorcm_realize;
|
|
dc->vmsd = &vmstate_integratorcm;
|
|
}
|
|
|
|
static void icp_pic_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->vmsd = &vmstate_icp_pic;
|
|
}
|
|
|
|
static void icp_control_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->vmsd = &vmstate_icp_control;
|
|
}
|
|
|
|
static const TypeInfo core_info = {
|
|
.name = TYPE_INTEGRATOR_CM,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(IntegratorCMState),
|
|
.instance_init = integratorcm_init,
|
|
.class_init = core_class_init,
|
|
};
|
|
|
|
static const TypeInfo icp_pic_info = {
|
|
.name = TYPE_INTEGRATOR_PIC,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(icp_pic_state),
|
|
.instance_init = icp_pic_init,
|
|
.class_init = icp_pic_class_init,
|
|
};
|
|
|
|
static const TypeInfo icp_ctrl_regs_info = {
|
|
.name = TYPE_ICP_CONTROL_REGS,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(ICPCtrlRegsState),
|
|
.instance_init = icp_control_init,
|
|
.class_init = icp_control_class_init,
|
|
};
|
|
|
|
static void integratorcp_register_types(void)
|
|
{
|
|
type_register_static(&icp_pic_info);
|
|
type_register_static(&core_info);
|
|
type_register_static(&icp_ctrl_regs_info);
|
|
}
|
|
|
|
type_init(integratorcp_register_types)
|