qemu/target/arm/tcg
Peter Maydell 7f3a3d3dc4 target/arm: Define and use new load_cpu_field_low32()
In several places in the 32-bit Arm translate.c, we try to use
load_cpu_field() to load from a CPUARMState field into a TCGv_i32
where the field is actually 64-bit. This works on little-endian
hosts, but gives the wrong half of the register on big-endian.

Add a new load_cpu_field_low32() which loads the low 32 bits
of a 64-bit field into a TCGv_i32. The new macro includes a
compile-time check against accidentally using it on a field
of the wrong size. Use it to fix the two places in the code
where we were using load_cpu_field() on a 64-bit field.

This fixes a bug where on big-endian hosts the guest would
crash after executing an ERET instruction, and a more corner
case one where some UNDEFs for attempted accesses to MSR
banked registers from Secure EL1 might go to the wrong EL.

Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230424153909.1419369-2-peter.maydell@linaro.org
2023-05-02 15:47:41 +01:00
..
a32-uncond.decode
a32.decode
cpu32.c target/arm: move cpu_tcg to tcg/cpu32.c 2023-05-02 10:54:31 +01:00
cpu64.c target/arm: move cpu_tcg to tcg/cpu32.c 2023-05-02 10:54:31 +01:00
crypto_helper.c
helper-a64.c gdbstub: move register helpers into standalone include 2023-03-07 20:44:08 +00:00
hflags.c target/arm: Move hflags code into the tcg directory 2023-02-27 13:27:04 +00:00
iwmmxt_helper.c
m_helper.c gdbstub: move register helpers into standalone include 2023-03-07 20:44:08 +00:00
m-nocp.decode
meson.build target/arm: move cpu_tcg to tcg/cpu32.c 2023-05-02 10:54:31 +01:00
mte_helper.c softmmu: Restrict cpu_check_watchpoint / address_matches to TCG accel 2023-03-28 15:24:06 -07:00
mve_helper.c
mve.decode
neon_helper.c
neon-dp.decode
neon-ls.decode
neon-shared.decode
op_helper.c
pauth_helper.c target/arm: Fix non-TCG build failure by inlining pauth_ptr_mask() 2023-04-03 16:12:29 +01:00
psci.c target/arm: Move psci.c into the tcg directory 2023-02-27 13:27:04 +00:00
sme_helper.c
sme-fa64.decode
sme.decode
sve_helper.c softmmu: Restrict cpu_check_watchpoint / address_matches to TCG accel 2023-03-28 15:24:06 -07:00
sve.decode
t16.decode
t32.decode
tlb_helper.c target/arm: Don't set ISV when reporting stage 1 faults in ESR_EL2 2023-04-20 10:21:16 +01:00
translate-a64.c target/arm: Avoid tcg_const_ptr in handle_rev 2023-03-13 07:03:39 -07:00
translate-a64.h target/arm: Drop new_tmp_a64_zero 2023-03-05 13:44:07 -08:00
translate-m-nocp.c target/arm: Drop tcg_temp_free from translator-m-nocp.c 2023-03-05 13:44:07 -08:00
translate-mve.c target/arm: Avoid tcg_const_* in translate-mve.c 2023-03-13 07:03:39 -07:00
translate-neon.c target/arm: Drop tcg_temp_free from translator-neon.c 2023-03-05 13:44:07 -08:00
translate-sme.c target/arm: Drop tcg_temp_free from translator-sme.c 2023-03-05 13:44:07 -08:00
translate-sve.c target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str} 2023-03-13 07:03:39 -07:00
translate-vfp.c target/arm: Create gen_set_rmode, gen_restore_rmode 2023-03-13 06:44:38 -07:00
translate.c target/arm: Define and use new load_cpu_field_low32() 2023-05-02 15:47:41 +01:00
translate.h target/arm: Create gen_set_rmode, gen_restore_rmode 2023-03-13 06:44:38 -07:00
vec_helper.c
vec_internal.h
vfp-uncond.decode
vfp.decode