7f0ec9893c
These definitions are specific to the A10 SoC and don't need to be exported to the different Allwinner peripherals. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20191230110953.25496-4-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
35 lines
759 B
C
35 lines
759 B
C
#ifndef HW_ARM_ALLWINNER_A10_H
|
|
#define HW_ARM_ALLWINNER_A10_H
|
|
|
|
#include "qemu/error-report.h"
|
|
#include "hw/char/serial.h"
|
|
#include "hw/arm/boot.h"
|
|
#include "hw/timer/allwinner-a10-pit.h"
|
|
#include "hw/intc/allwinner-a10-pic.h"
|
|
#include "hw/net/allwinner_emac.h"
|
|
#include "hw/ide/ahci.h"
|
|
|
|
#include "target/arm/cpu.h"
|
|
|
|
|
|
#define AW_A10_SDRAM_BASE 0x40000000
|
|
|
|
#define TYPE_AW_A10 "allwinner-a10"
|
|
#define AW_A10(obj) OBJECT_CHECK(AwA10State, (obj), TYPE_AW_A10)
|
|
|
|
typedef struct AwA10State {
|
|
/*< private >*/
|
|
DeviceState parent_obj;
|
|
/*< public >*/
|
|
|
|
ARMCPU cpu;
|
|
qemu_irq irq[AW_A10_PIC_INT_NR];
|
|
AwA10PITState timer;
|
|
AwA10PICState intc;
|
|
AwEmacState emac;
|
|
AllwinnerAHCIState sata;
|
|
MemoryRegion sram_a;
|
|
} AwA10State;
|
|
|
|
#endif
|