qemu/hw/riscv
Markus Armbruster 7eecec7d12 qom: Drop object_property_set_description() parameter @errp
object_property_set_description() and
object_class_property_set_description() fail only when property @name
is not found.

There are 85 calls of object_property_set_description() and
object_class_property_set_description().  None of them can fail:

* 84 immediately follow the creation of the property.

* The one in spapr_rng_instance_init() refers to a property created in
  spapr_rng_class_init(), from spapr_rng_properties[].

Every one of them still gets to decide what to pass for @errp.

51 calls pass &error_abort, 32 calls pass NULL, one receives the error
and propagates it to &error_abort, and one propagates it to
&error_fatal.  I'm actually surprised none of them violates the Error
API.

What are we gaining by letting callers handle the "property not found"
error?  Use when the property is not known to exist is simpler: you
don't have to guard the call with a check.  We haven't found such a
use in 5+ years.  Until we do, let's make life a bit simpler and drop
the @errp parameter.

Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200505152926.18877-8-armbru@redhat.com>
[One semantic rebase conflict resolved]
2020-05-15 07:06:49 +02:00
..
boot.c hw/riscv: Add optional symbol callback ptr to riscv_load_firmware() 2020-04-29 13:16:38 -07:00
Kconfig riscv: virt: Use Goldfish RTC device 2020-02-10 12:01:38 -08:00
Makefile.objs riscv: sifive: Implement a model for SiFive FU540 OTP 2019-09-17 08:42:49 -07:00
riscv_hart.c qdev: set properties with device_class_set_props() 2020-01-24 20:59:15 +01:00
riscv_htif.c chardev: Use QEMUChrEvent enum in IOEventHandler typedef 2020-01-08 11:15:35 +01:00
sifive_clint.c hw/riscv: Provide rdtime callback for TCG in CLINT emulation 2020-02-27 13:46:37 -08:00
sifive_e_prci.c riscv: sifive_e: prci: Update the PRCI register block size 2019-09-17 08:42:46 -07:00
sifive_e.c riscv: sifive_e: Support changing CPU type 2020-04-29 13:16:37 -07:00
sifive_gpio.c Include migration/vmstate.h less 2019-08-16 13:31:52 +02:00
sifive_plic.c qdev: set properties with device_class_set_props() 2020-01-24 20:59:15 +01:00
sifive_test.c riscv: hw: Remove the unnecessary include of target/riscv/cpu.h 2019-09-17 08:42:45 -07:00
sifive_u_otp.c qdev: set properties with device_class_set_props() 2020-01-24 20:59:15 +01:00
sifive_u_prci.c riscv: sifive: Implement PRCI model for FU540 2019-09-17 08:42:47 -07:00
sifive_u.c qom: Drop object_property_set_description() parameter @errp 2020-05-15 07:06:49 +02:00
sifive_uart.c chardev: Use QEMUChrEvent enum in IOEventHandler typedef 2020-01-08 11:15:35 +01:00
spike.c hw/riscv/spike: Allow more than one CPUs 2020-04-29 13:16:38 -07:00
trace-events SiFive RISC-V GPIO Device 2019-05-24 11:58:30 -07:00
virt.c hw/riscv: Add optional symbol callback ptr to riscv_load_firmware() 2020-04-29 13:16:38 -07:00