7e6b5497ea
hw/char/serial currently contains the implementation of both TYPE_SERIAL and TYPE_SERIAL_MM. According to serial_class_init(), TYPE_SERIAL is an internal class while TYPE_SERIAL_MM is used by numerous machine types directly. Let's move the latter into its own module which makes the dependencies more obvious and the code more tidy. The includes and the dependencies have been converted mechanically except in the hw/char directories which were updated manually. The result was compile-tested. Now, only hw/char makes direct use of TYPE_SERIAL: # grep -r -e "select SERIAL" | grep -v SERIAL_ hw/char/Kconfig: select SERIAL hw/char/Kconfig: select SERIAL hw/char/Kconfig: select SERIAL hw/char/Kconfig: select SERIAL hw/char/Kconfig: select SERIAL # grep -r -e "/serial\\.h" include/hw/char/serial-mm.h:#include "hw/char/serial.h" hw/char/serial-pci-multi.c:#include "hw/char/serial.h" hw/char/serial.c:#include "hw/char/serial.h" hw/char/serial-isa.c:#include "hw/char/serial.h" hw/char/serial-pci.c:#include "hw/char/serial.h" Tested-by: Andrew Jeffery <andrew@codeconstruct.com.au> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Link: https://lore.kernel.org/r/20240905073832.16222-4-shentey@gmail.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
372 lines
12 KiB
C
372 lines
12 KiB
C
/*
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* OpenRISC simulator for use as an IIS.
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*
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* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
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* Feng Gao <gf91597@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "hw/irq.h"
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#include "hw/boards.h"
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#include "hw/char/serial-mm.h"
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#include "net/net.h"
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#include "hw/openrisc/boot.h"
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#include "hw/qdev-properties.h"
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#include "exec/address-spaces.h"
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#include "sysemu/device_tree.h"
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#include "sysemu/sysemu.h"
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#include "hw/sysbus.h"
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#include "sysemu/qtest.h"
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#include "sysemu/reset.h"
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#include "hw/core/split-irq.h"
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#include <libfdt.h>
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#define KERNEL_LOAD_ADDR 0x100
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#define OR1KSIM_CPUS_MAX 4
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#define OR1KSIM_CLK_MHZ 20000000
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#define TYPE_OR1KSIM_MACHINE MACHINE_TYPE_NAME("or1k-sim")
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#define OR1KSIM_MACHINE(obj) \
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OBJECT_CHECK(Or1ksimState, (obj), TYPE_OR1KSIM_MACHINE)
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typedef struct Or1ksimState {
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/*< private >*/
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MachineState parent_obj;
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/*< public >*/
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void *fdt;
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int fdt_size;
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} Or1ksimState;
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enum {
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OR1KSIM_DRAM,
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OR1KSIM_UART,
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OR1KSIM_ETHOC,
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OR1KSIM_OMPIC,
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};
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enum {
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OR1KSIM_OMPIC_IRQ = 1,
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OR1KSIM_UART_IRQ = 2,
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OR1KSIM_ETHOC_IRQ = 4,
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};
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enum {
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OR1KSIM_UART_COUNT = 4
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};
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static const struct MemmapEntry {
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hwaddr base;
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hwaddr size;
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} or1ksim_memmap[] = {
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[OR1KSIM_DRAM] = { 0x00000000, 0 },
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[OR1KSIM_UART] = { 0x90000000, 0x100 },
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[OR1KSIM_ETHOC] = { 0x92000000, 0x800 },
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[OR1KSIM_OMPIC] = { 0x98000000, OR1KSIM_CPUS_MAX * 8 },
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};
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static struct openrisc_boot_info {
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uint32_t bootstrap_pc;
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uint32_t fdt_addr;
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} boot_info;
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static void main_cpu_reset(void *opaque)
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{
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OpenRISCCPU *cpu = opaque;
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CPUState *cs = CPU(cpu);
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cpu_reset(CPU(cpu));
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cpu_set_pc(cs, boot_info.bootstrap_pc);
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cpu_set_gpr(&cpu->env, 3, boot_info.fdt_addr);
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}
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static qemu_irq get_cpu_irq(OpenRISCCPU *cpus[], int cpunum, int irq_pin)
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{
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return qdev_get_gpio_in_named(DEVICE(cpus[cpunum]), "IRQ", irq_pin);
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}
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static void openrisc_create_fdt(Or1ksimState *state,
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const struct MemmapEntry *memmap,
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int num_cpus, uint64_t mem_size,
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const char *cmdline)
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{
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void *fdt;
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int cpu;
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char *nodename;
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int pic_ph;
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fdt = state->fdt = create_device_tree(&state->fdt_size);
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if (!fdt) {
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error_report("create_device_tree() failed");
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exit(1);
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}
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qemu_fdt_setprop_string(fdt, "/", "compatible", "opencores,or1ksim");
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qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x1);
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qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x1);
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nodename = g_strdup_printf("/memory@%" HWADDR_PRIx,
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memmap[OR1KSIM_DRAM].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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memmap[OR1KSIM_DRAM].base, mem_size);
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qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
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g_free(nodename);
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qemu_fdt_add_subnode(fdt, "/cpus");
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qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
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for (cpu = 0; cpu < num_cpus; cpu++) {
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nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_string(fdt, nodename, "compatible",
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"opencores,or1200-rtlsvn481");
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qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
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qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
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OR1KSIM_CLK_MHZ);
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g_free(nodename);
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}
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nodename = (char *)"/pic";
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qemu_fdt_add_subnode(fdt, nodename);
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pic_ph = qemu_fdt_alloc_phandle(fdt);
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qemu_fdt_setprop_string(fdt, nodename, "compatible",
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"opencores,or1k-pic-level");
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qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
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qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop_cell(fdt, nodename, "phandle", pic_ph);
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qemu_fdt_setprop_cell(fdt, "/", "interrupt-parent", pic_ph);
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qemu_fdt_add_subnode(fdt, "/chosen");
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if (cmdline) {
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qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
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}
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/* Create aliases node for use by devices. */
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qemu_fdt_add_subnode(fdt, "/aliases");
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}
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static void openrisc_sim_net_init(Or1ksimState *state, hwaddr base, hwaddr size,
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int num_cpus, OpenRISCCPU *cpus[],
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int irq_pin)
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{
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void *fdt = state->fdt;
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DeviceState *dev;
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SysBusDevice *s;
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char *nodename;
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int i;
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dev = qemu_create_nic_device("open_eth", true, NULL);
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if (!dev) {
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return;
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}
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s = SYS_BUS_DEVICE(dev);
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sysbus_realize_and_unref(s, &error_fatal);
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if (num_cpus > 1) {
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DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ);
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qdev_prop_set_uint32(splitter, "num-lines", num_cpus);
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qdev_realize_and_unref(splitter, NULL, &error_fatal);
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for (i = 0; i < num_cpus; i++) {
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qdev_connect_gpio_out(splitter, i, get_cpu_irq(cpus, i, irq_pin));
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}
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sysbus_connect_irq(s, 0, qdev_get_gpio_in(splitter, 0));
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} else {
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sysbus_connect_irq(s, 0, get_cpu_irq(cpus, 0, irq_pin));
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}
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sysbus_mmio_map(s, 0, base);
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sysbus_mmio_map(s, 1, base + 0x400);
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/* Init device tree node for ethoc. */
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nodename = g_strdup_printf("/ethoc@%" HWADDR_PRIx, base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "opencores,ethoc");
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qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
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qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
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qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0);
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qemu_fdt_setprop_string(fdt, "/aliases", "enet0", nodename);
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g_free(nodename);
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}
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static void openrisc_sim_ompic_init(Or1ksimState *state, hwaddr base,
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hwaddr size, int num_cpus,
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OpenRISCCPU *cpus[], int irq_pin)
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{
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void *fdt = state->fdt;
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DeviceState *dev;
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SysBusDevice *s;
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char *nodename;
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int i;
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dev = qdev_new("or1k-ompic");
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qdev_prop_set_uint32(dev, "num-cpus", num_cpus);
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s = SYS_BUS_DEVICE(dev);
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sysbus_realize_and_unref(s, &error_fatal);
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for (i = 0; i < num_cpus; i++) {
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sysbus_connect_irq(s, i, get_cpu_irq(cpus, i, irq_pin));
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}
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sysbus_mmio_map(s, 0, base);
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/* Add device tree node for ompic. */
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nodename = g_strdup_printf("/ompic@%" HWADDR_PRIx, base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "openrisc,ompic");
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qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
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qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 0);
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qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
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g_free(nodename);
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}
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static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base,
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hwaddr size, int num_cpus,
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OpenRISCCPU *cpus[], int irq_pin,
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int uart_idx)
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{
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void *fdt = state->fdt;
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char *nodename;
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qemu_irq serial_irq;
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char alias[sizeof("uart0")];
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int i;
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if (num_cpus > 1) {
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DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ);
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qdev_prop_set_uint32(splitter, "num-lines", num_cpus);
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qdev_realize_and_unref(splitter, NULL, &error_fatal);
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for (i = 0; i < num_cpus; i++) {
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qdev_connect_gpio_out(splitter, i, get_cpu_irq(cpus, i, irq_pin));
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}
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serial_irq = qdev_get_gpio_in(splitter, 0);
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} else {
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serial_irq = get_cpu_irq(cpus, 0, irq_pin);
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}
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serial_mm_init(get_system_memory(), base, 0, serial_irq, 115200,
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serial_hd(OR1KSIM_UART_COUNT - uart_idx - 1),
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DEVICE_NATIVE_ENDIAN);
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/* Add device tree node for serial. */
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nodename = g_strdup_printf("/serial@%" HWADDR_PRIx, base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a");
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qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
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qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
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qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", OR1KSIM_CLK_MHZ);
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qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0);
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/* The /chosen node is created during fdt creation. */
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qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
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snprintf(alias, sizeof(alias), "uart%d", uart_idx);
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qemu_fdt_setprop_string(fdt, "/aliases", alias, nodename);
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g_free(nodename);
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}
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static void openrisc_sim_init(MachineState *machine)
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{
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ram_addr_t ram_size = machine->ram_size;
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const char *kernel_filename = machine->kernel_filename;
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OpenRISCCPU *cpus[OR1KSIM_CPUS_MAX] = {};
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Or1ksimState *state = OR1KSIM_MACHINE(machine);
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MemoryRegion *ram;
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hwaddr load_addr;
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int n;
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unsigned int smp_cpus = machine->smp.cpus;
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assert(smp_cpus >= 1 && smp_cpus <= OR1KSIM_CPUS_MAX);
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for (n = 0; n < smp_cpus; n++) {
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cpus[n] = OPENRISC_CPU(cpu_create(machine->cpu_type));
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if (cpus[n] == NULL) {
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fprintf(stderr, "Unable to find CPU definition!\n");
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exit(1);
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}
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cpu_openrisc_clock_init(cpus[n]);
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qemu_register_reset(main_cpu_reset, cpus[n]);
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}
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ram = g_malloc(sizeof(*ram));
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memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_fatal);
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memory_region_add_subregion(get_system_memory(), 0, ram);
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openrisc_create_fdt(state, or1ksim_memmap, smp_cpus, machine->ram_size,
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machine->kernel_cmdline);
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openrisc_sim_net_init(state, or1ksim_memmap[OR1KSIM_ETHOC].base,
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or1ksim_memmap[OR1KSIM_ETHOC].size,
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smp_cpus, cpus,
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OR1KSIM_ETHOC_IRQ);
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if (smp_cpus > 1) {
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openrisc_sim_ompic_init(state, or1ksim_memmap[OR1KSIM_OMPIC].base,
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or1ksim_memmap[OR1KSIM_OMPIC].size,
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smp_cpus, cpus, OR1KSIM_OMPIC_IRQ);
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}
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for (n = 0; n < OR1KSIM_UART_COUNT; ++n)
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openrisc_sim_serial_init(state, or1ksim_memmap[OR1KSIM_UART].base +
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or1ksim_memmap[OR1KSIM_UART].size * n,
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or1ksim_memmap[OR1KSIM_UART].size,
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smp_cpus, cpus, OR1KSIM_UART_IRQ, n);
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load_addr = openrisc_load_kernel(ram_size, kernel_filename,
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&boot_info.bootstrap_pc);
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if (load_addr > 0) {
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if (machine->initrd_filename) {
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load_addr = openrisc_load_initrd(state->fdt,
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machine->initrd_filename,
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load_addr, machine->ram_size);
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}
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boot_info.fdt_addr = openrisc_load_fdt(state->fdt, load_addr,
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machine->ram_size);
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}
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}
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static void openrisc_sim_machine_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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mc->desc = "or1k simulation";
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mc->init = openrisc_sim_init;
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mc->max_cpus = OR1KSIM_CPUS_MAX;
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mc->is_default = true;
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mc->default_cpu_type = OPENRISC_CPU_TYPE_NAME("or1200");
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}
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static const TypeInfo or1ksim_machine_typeinfo = {
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.name = TYPE_OR1KSIM_MACHINE,
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.parent = TYPE_MACHINE,
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.class_init = openrisc_sim_machine_init,
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.instance_size = sizeof(Or1ksimState),
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};
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static void or1ksim_machine_init_register_types(void)
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{
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type_register_static(&or1ksim_machine_typeinfo);
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}
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type_init(or1ksim_machine_init_register_types)
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