qemu/target/riscv/insn_trans
Daniel Henrique Barboza 7e53e3ddf6 target/riscv: always clear vstart in whole vec move insns
These insns have 2 paths: we'll either have vstart already cleared if
vstart_eq_zero or we'll do a brcond to check if vstart >= maxsz to call
the 'vmvr_v' helper. The helper will clear vstart if it executes until
the end, or if vstart >= vl.

For starters, the check itself is wrong: we're checking vstart >= maxsz,
when in fact we should use vstart in bytes, or 'startb' like 'vmvr_v' is
calling, to do the comparison. But even after fixing the comparison we'll
still need to clear vstart in the end, which isn't happening too.

We want to make the helpers responsible to manage vstart, including
these corner cases, precisely to avoid these situations:

- remove the wrong vstart >= maxsz cond from the translation;
- add a 'startb >= maxsz' cond in 'vmvr_v', and clear vstart if that
  happens.

This way we're now sure that vstart is being cleared in the end of the
execution, regardless of the path taken.

Fixes: f714361ed7 ("target/riscv: rvv-1.0: implement vstart CSR")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240314175704.478276-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-03-22 15:16:54 +10:00
..
trans_privileged.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rva.c.inc RISC-V: Add support for Ztso 2024-03-08 19:47:48 +10:00
trans_rvb.c.inc target/riscv: Drop tcg_temp_free 2023-03-05 13:44:08 -08:00
trans_rvbf16.c.inc target/riscv/insn_trans/trans_rvbf16.c.inc: use cpu->cfg.vlenb 2024-02-09 20:43:14 +10:00
trans_rvd.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvf.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvh.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvi.c.inc RISC-V: Add support for Ztso 2024-03-08 19:47:48 +10:00
trans_rvk.c.inc target/riscv: Drop tcg_temp_free 2023-03-05 13:44:08 -08:00
trans_rvm.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvv.c.inc target/riscv: always clear vstart in whole vec move insns 2024-03-22 15:16:54 +10:00
trans_rvvk.c.inc target/riscv/insn_trans/trans_rvvk.c.inc: use 'vlenb' 2024-02-09 20:43:14 +10:00
trans_rvzacas.c.inc target/riscv: Add support for Zacas extension 2024-01-10 18:47:47 +10:00
trans_rvzawrs.c.inc target/riscv: Change gen_set_pc_imm to gen_update_pc 2023-06-13 17:35:20 +10:00
trans_rvzce.c.inc target/riscv: Update $ra with current $pc in trans_cm_jalt() 2024-03-08 15:37:20 +10:00
trans_rvzfa.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvzfh.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_rvzicbo.c.inc target/riscv: rename ext_icboz to ext_zicboz 2023-11-07 11:02:17 +10:00
trans_rvzicond.c.inc target/riscv: refactor Zicond support 2023-05-05 10:49:50 +10:00
trans_svinval.c.inc tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
trans_xthead.c.inc target/riscv: Enable xtheadsync under user mode 2024-02-09 20:43:14 +10:00
trans_xventanacondops.c.inc target/riscv: redirect XVentanaCondOps to use the Zicond functions 2023-05-05 10:49:50 +10:00