Bastian Koppelmann 7e45a682ed target/riscv: Convert RV64I load/store insns to decodetree ... this splits the 64-bit only instructions into its own decode file such that we generate the decoder for these instructions only for the RISC-V 64 bit target. Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>		2019-03-13 10:34:06 +01:00
..
insn_trans	target/riscv: Convert RV64I load/store insns to decodetree	2019-03-13 10:34:06 +01:00
cpu_bits.h	RISC-V: Add misa runtime write support	2019-02-11 15:56:22 -08:00
cpu_helper.c	RISC-V: Use riscv prefix consistently on cpu helpers	2019-02-11 15:56:21 -08:00
cpu_user.h	RISC-V Linux User Emulation	2018-03-07 08:30:28 +13:00
cpu.c	RISC-V: Add misa runtime write support	2019-02-11 15:56:22 -08:00
cpu.h	RISC-V: Add misa runtime write support	2019-02-11 15:56:22 -08:00
csr.c	target/riscv: fix counter-enable checks in ctr()	2019-02-11 15:56:22 -08:00
fpu_helper.c	RISC-V: Use riscv prefix consistently on cpu helpers	2019-02-11 15:56:21 -08:00
gdbstub.c	RISC-V: Implement modular CSR helper interface	2019-01-08 13:59:09 -08:00
helper.h	RISC-V CPU Helpers	2018-03-07 08:30:28 +13:00
insn32-64.decode	target/riscv: Convert RV64I load/store insns to decodetree	2019-03-13 10:34:06 +01:00
insn32.decode	target/riscv: Convert RV32I load/store insns to decodetree	2019-03-13 10:34:06 +01:00
instmap.h	RISC-V TCG Code Generation	2018-03-07 08:30:28 +13:00
Makefile.objs	target/riscv: Convert RV64I load/store insns to decodetree	2019-03-13 10:34:06 +01:00
op_helper.c	RISC-V: Use riscv prefix consistently on cpu helpers	2019-02-11 15:56:21 -08:00
pmp.c	target/riscv/pmp.c: Fix pmp_decode_napot()	2018-12-20 12:26:39 -08:00
pmp.h	RISC-V Physical Memory Protection	2018-03-07 08:30:28 +13:00
translate.c	target/riscv: Convert RV64I load/store insns to decodetree	2019-03-13 10:34:06 +01:00