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7dd8c9af0d
qemu/target-arm
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Fabian Aggeler 7dd8c9af0d target-arm: make TTBR0/1 banked 
Adds secure and non-secure bank register suport for TTBR0 and TTBR1.
Changes include adding secure and non-secure instances of ttbr0 and ttbr1 as
well as a CP register definition for TTBR0_EL3.  Added a union containing
both EL based array fields and secure and non-secure fields mapped to them.
Updated accesses to use A32_BANKED_CURRENT_REG_GET macro.

Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1416242878-876-17-git-send-email-greg.bellows@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-11 12:07:51 +00:00
..
arm_ldst.h softmmu: introduce cpu_ldst.h 2014-06-05 16:10:33 +02:00
arm-semi.c Pass semihosting exit code back to system. 2014-12-11 12:07:48 +00:00
cpu64.c target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any" 2014-10-24 12:19:13 +01:00
cpu-qom.h target-arm: add emulation of PSCI calls for system emulation 2014-10-24 12:19:13 +01:00
cpu.c target-arm: add SCTLR_EL3 and make SCTLR banked 2014-12-11 12:07:50 +00:00
cpu.h target-arm: make TTBR0/1 banked 2014-12-11 12:07:51 +00:00
crypto_helper.c target-arm: Use Common Tables in AES Instructions 2014-06-16 13:24:33 +02:00
gdbstub64.c target-arm/gdbstub64.c: remove useless 'break' statement. 2014-04-17 21:34:06 +01:00
gdbstub.c cpu: Introduce CPUClass::gdb_{read,write}_register() 2013-07-27 00:04:17 +02:00
helper-a64.c target-arm: rename arm_current_pl to arm_current_el 2014-10-24 12:19:14 +01:00
helper-a64.h target-arm: A64: Implement CRC instructions 2014-06-09 16:06:12 +01:00
helper.c target-arm: make TTBR0/1 banked 2014-12-11 12:07:51 +00:00
helper.h target-arm: A64: Emulate the SMC insn 2014-09-29 18:48:50 +01:00
internals.h target-arm: rename arm_current_pl to arm_current_el 2014-10-24 12:19:14 +01:00
iwmmxt_helper.c target-arm: Delete unused iwmmxt_msadb helper 2014-06-09 16:06:12 +01:00
kvm32.c target-arm: add secure state bit to CPREG hash 2014-12-11 12:07:49 +00:00
kvm64.c target-arm: A64: Break out aarch64_save/restore_sp 2014-08-04 14:41:54 +01:00
kvm_arm.h target-arm: Common kvm_arm_vcpu_init() for KVM ARM and KVM ARM64 2014-06-19 18:33:02 +01:00
kvm-consts.h target-arm: add missing PSCI constants needed for PSCI emulation 2014-10-24 12:19:12 +01:00
kvm-stub.c target-arm: Initialize cpreg list from KVM when using KVM 2013-06-25 18:16:10 +01:00
kvm.c target-arm: Common kvm_arm_vcpu_init() for KVM ARM and KVM ARM64 2014-06-19 18:33:02 +01:00
machine.c target-arm: increase arrays of registers R13 & R14 2014-10-24 12:19:14 +01:00
Makefile.objs target-arm: add emulation of PSCI calls for system emulation 2014-10-24 12:19:13 +01:00
neon_helper.c target-arm: add support for v8 VMULL.P64 instruction 2014-06-09 16:06:11 +01:00
op_addsub.h Correct spelling of licensed 2011-07-23 11:26:12 -05:00
op_helper.c target-arm: add SCTLR_EL3 and make SCTLR banked 2014-12-11 12:07:50 +00:00
psci.c target-arm: add emulation of PSCI calls for system emulation 2014-10-24 12:19:13 +01:00
translate-a64.c target-arm: A64: remove redundant store 2014-11-02 10:04:34 +03:00
translate.c target-arm: add secure state bit to CPREG hash 2014-12-11 12:07:49 +00:00
translate.h target-arm: add non-secure Translation Block flag 2014-12-11 12:07:48 +00:00