09a333ee3d
Coverity points out in CID 1390588 that the test for sh == 0
in sdram_size() can never fire, because we calculate sh with
sh = 1024 - ((bcr >> 6) & 0x3ff);
which must result in a value between 1 and 1024 inclusive.
Without the relevant manual for the SoC, we're not completely
sure of the correct behaviour here, but we can remove the
dead code without changing how QEMU currently behaves.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
1380 lines
38 KiB
C
1380 lines
38 KiB
C
/*
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* QEMU PowerPC 440 embedded processors emulation
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*
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* Copyright (c) 2012 François Revol
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* Copyright (c) 2016-2018 BALATON Zoltan
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*
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* This work is licensed under the GNU GPL license version 2 or later.
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*
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qemu-common.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "hw/hw.h"
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#include "exec/address-spaces.h"
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#include "exec/memory.h"
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#include "hw/ppc/ppc.h"
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#include "hw/pci/pci.h"
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#include "sysemu/block-backend.h"
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#include "ppc440.h"
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/*****************************************************************************/
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/* L2 Cache as SRAM */
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/* FIXME:fix names */
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enum {
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DCR_L2CACHE_BASE = 0x30,
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DCR_L2CACHE_CFG = DCR_L2CACHE_BASE,
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DCR_L2CACHE_CMD,
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DCR_L2CACHE_ADDR,
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DCR_L2CACHE_DATA,
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DCR_L2CACHE_STAT,
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DCR_L2CACHE_CVER,
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DCR_L2CACHE_SNP0,
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DCR_L2CACHE_SNP1,
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DCR_L2CACHE_END = DCR_L2CACHE_SNP1,
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};
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/* base is 460ex-specific, cf. U-Boot, ppc4xx-isram.h */
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enum {
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DCR_ISRAM0_BASE = 0x20,
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DCR_ISRAM0_SB0CR = DCR_ISRAM0_BASE,
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DCR_ISRAM0_SB1CR,
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DCR_ISRAM0_SB2CR,
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DCR_ISRAM0_SB3CR,
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DCR_ISRAM0_BEAR,
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DCR_ISRAM0_BESR0,
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DCR_ISRAM0_BESR1,
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DCR_ISRAM0_PMEG,
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DCR_ISRAM0_CID,
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DCR_ISRAM0_REVID,
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DCR_ISRAM0_DPC,
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DCR_ISRAM0_END = DCR_ISRAM0_DPC
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};
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enum {
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DCR_ISRAM1_BASE = 0xb0,
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DCR_ISRAM1_SB0CR = DCR_ISRAM1_BASE,
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/* single bank */
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DCR_ISRAM1_BEAR = DCR_ISRAM1_BASE + 0x04,
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DCR_ISRAM1_BESR0,
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DCR_ISRAM1_BESR1,
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DCR_ISRAM1_PMEG,
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DCR_ISRAM1_CID,
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DCR_ISRAM1_REVID,
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DCR_ISRAM1_DPC,
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DCR_ISRAM1_END = DCR_ISRAM1_DPC
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};
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typedef struct ppc4xx_l2sram_t {
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MemoryRegion bank[4];
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uint32_t l2cache[8];
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uint32_t isram0[11];
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} ppc4xx_l2sram_t;
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#ifdef MAP_L2SRAM
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static void l2sram_update_mappings(ppc4xx_l2sram_t *l2sram,
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uint32_t isarc, uint32_t isacntl,
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uint32_t dsarc, uint32_t dsacntl)
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{
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if (l2sram->isarc != isarc ||
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(l2sram->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
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if (l2sram->isacntl & 0x80000000) {
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/* Unmap previously assigned memory region */
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memory_region_del_subregion(get_system_memory(),
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&l2sram->isarc_ram);
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}
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if (isacntl & 0x80000000) {
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/* Map new instruction memory region */
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memory_region_add_subregion(get_system_memory(), isarc,
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&l2sram->isarc_ram);
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}
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}
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if (l2sram->dsarc != dsarc ||
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(l2sram->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
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if (l2sram->dsacntl & 0x80000000) {
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/* Beware not to unmap the region we just mapped */
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if (!(isacntl & 0x80000000) || l2sram->dsarc != isarc) {
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/* Unmap previously assigned memory region */
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memory_region_del_subregion(get_system_memory(),
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&l2sram->dsarc_ram);
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}
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}
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if (dsacntl & 0x80000000) {
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/* Beware not to remap the region we just mapped */
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if (!(isacntl & 0x80000000) || dsarc != isarc) {
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/* Map new data memory region */
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memory_region_add_subregion(get_system_memory(), dsarc,
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&l2sram->dsarc_ram);
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}
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}
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}
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}
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#endif
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static uint32_t dcr_read_l2sram(void *opaque, int dcrn)
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{
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ppc4xx_l2sram_t *l2sram = opaque;
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uint32_t ret = 0;
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switch (dcrn) {
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case DCR_L2CACHE_CFG:
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case DCR_L2CACHE_CMD:
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case DCR_L2CACHE_ADDR:
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case DCR_L2CACHE_DATA:
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case DCR_L2CACHE_STAT:
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case DCR_L2CACHE_CVER:
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case DCR_L2CACHE_SNP0:
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case DCR_L2CACHE_SNP1:
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ret = l2sram->l2cache[dcrn - DCR_L2CACHE_BASE];
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break;
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case DCR_ISRAM0_SB0CR:
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case DCR_ISRAM0_SB1CR:
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case DCR_ISRAM0_SB2CR:
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case DCR_ISRAM0_SB3CR:
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case DCR_ISRAM0_BEAR:
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case DCR_ISRAM0_BESR0:
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case DCR_ISRAM0_BESR1:
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case DCR_ISRAM0_PMEG:
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case DCR_ISRAM0_CID:
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case DCR_ISRAM0_REVID:
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case DCR_ISRAM0_DPC:
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ret = l2sram->isram0[dcrn - DCR_ISRAM0_BASE];
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break;
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default:
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break;
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}
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return ret;
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}
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static void dcr_write_l2sram(void *opaque, int dcrn, uint32_t val)
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{
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/*ppc4xx_l2sram_t *l2sram = opaque;*/
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/* FIXME: Actually handle L2 cache mapping */
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switch (dcrn) {
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case DCR_L2CACHE_CFG:
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case DCR_L2CACHE_CMD:
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case DCR_L2CACHE_ADDR:
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case DCR_L2CACHE_DATA:
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case DCR_L2CACHE_STAT:
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case DCR_L2CACHE_CVER:
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case DCR_L2CACHE_SNP0:
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case DCR_L2CACHE_SNP1:
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/*l2sram->l2cache[dcrn - DCR_L2CACHE_BASE] = val;*/
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break;
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case DCR_ISRAM0_SB0CR:
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case DCR_ISRAM0_SB1CR:
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case DCR_ISRAM0_SB2CR:
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case DCR_ISRAM0_SB3CR:
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case DCR_ISRAM0_BEAR:
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case DCR_ISRAM0_BESR0:
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case DCR_ISRAM0_BESR1:
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case DCR_ISRAM0_PMEG:
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case DCR_ISRAM0_CID:
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case DCR_ISRAM0_REVID:
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case DCR_ISRAM0_DPC:
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/*l2sram->isram0[dcrn - DCR_L2CACHE_BASE] = val;*/
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break;
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case DCR_ISRAM1_SB0CR:
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case DCR_ISRAM1_BEAR:
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case DCR_ISRAM1_BESR0:
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case DCR_ISRAM1_BESR1:
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case DCR_ISRAM1_PMEG:
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case DCR_ISRAM1_CID:
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case DCR_ISRAM1_REVID:
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case DCR_ISRAM1_DPC:
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/*l2sram->isram1[dcrn - DCR_L2CACHE_BASE] = val;*/
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break;
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}
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/*l2sram_update_mappings(l2sram, isarc, isacntl, dsarc, dsacntl);*/
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}
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static void l2sram_reset(void *opaque)
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{
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ppc4xx_l2sram_t *l2sram = opaque;
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memset(l2sram->l2cache, 0, sizeof(l2sram->l2cache));
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l2sram->l2cache[DCR_L2CACHE_STAT - DCR_L2CACHE_BASE] = 0x80000000;
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memset(l2sram->isram0, 0, sizeof(l2sram->isram0));
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/*l2sram_update_mappings(l2sram, isarc, isacntl, dsarc, dsacntl);*/
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}
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void ppc4xx_l2sram_init(CPUPPCState *env)
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{
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ppc4xx_l2sram_t *l2sram;
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l2sram = g_malloc0(sizeof(*l2sram));
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/* XXX: Size is 4*64kB for 460ex, cf. U-Boot, ppc4xx-isram.h */
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memory_region_init_ram(&l2sram->bank[0], NULL, "ppc4xx.l2sram_bank0",
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64 * KiB, &error_abort);
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memory_region_init_ram(&l2sram->bank[1], NULL, "ppc4xx.l2sram_bank1",
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64 * KiB, &error_abort);
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memory_region_init_ram(&l2sram->bank[2], NULL, "ppc4xx.l2sram_bank2",
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64 * KiB, &error_abort);
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memory_region_init_ram(&l2sram->bank[3], NULL, "ppc4xx.l2sram_bank3",
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64 * KiB, &error_abort);
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qemu_register_reset(&l2sram_reset, l2sram);
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ppc_dcr_register(env, DCR_L2CACHE_CFG,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_L2CACHE_CMD,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_L2CACHE_ADDR,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_L2CACHE_DATA,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_L2CACHE_STAT,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_L2CACHE_CVER,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_L2CACHE_SNP0,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_L2CACHE_SNP1,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_ISRAM0_SB0CR,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_ISRAM0_SB1CR,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_ISRAM0_SB2CR,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_ISRAM0_SB3CR,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_ISRAM0_PMEG,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_ISRAM0_DPC,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_ISRAM1_SB0CR,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_ISRAM1_PMEG,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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ppc_dcr_register(env, DCR_ISRAM1_DPC,
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l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
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}
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/*****************************************************************************/
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/* Clocking Power on Reset */
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enum {
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CPR0_CFGADDR = 0xC,
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CPR0_CFGDATA = 0xD,
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CPR0_PLLD = 0x060,
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CPR0_PLBED = 0x080,
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CPR0_OPBD = 0x0C0,
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CPR0_PERD = 0x0E0,
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CPR0_AHBD = 0x100,
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};
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typedef struct ppc4xx_cpr_t {
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uint32_t addr;
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} ppc4xx_cpr_t;
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static uint32_t dcr_read_cpr(void *opaque, int dcrn)
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{
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ppc4xx_cpr_t *cpr = opaque;
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uint32_t ret = 0;
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switch (dcrn) {
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case CPR0_CFGADDR:
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ret = cpr->addr;
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break;
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case CPR0_CFGDATA:
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switch (cpr->addr) {
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case CPR0_PLLD:
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ret = (0xb5 << 24) | (1 << 16) | (9 << 8);
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break;
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case CPR0_PLBED:
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ret = (5 << 24);
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break;
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case CPR0_OPBD:
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ret = (2 << 24);
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break;
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case CPR0_PERD:
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case CPR0_AHBD:
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ret = (1 << 24);
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break;
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default:
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break;
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}
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break;
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default:
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break;
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}
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return ret;
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}
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static void dcr_write_cpr(void *opaque, int dcrn, uint32_t val)
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{
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ppc4xx_cpr_t *cpr = opaque;
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switch (dcrn) {
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case CPR0_CFGADDR:
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cpr->addr = val;
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break;
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case CPR0_CFGDATA:
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break;
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default:
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break;
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}
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}
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static void ppc4xx_cpr_reset(void *opaque)
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{
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ppc4xx_cpr_t *cpr = opaque;
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cpr->addr = 0;
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}
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void ppc4xx_cpr_init(CPUPPCState *env)
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{
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ppc4xx_cpr_t *cpr;
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cpr = g_malloc0(sizeof(*cpr));
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ppc_dcr_register(env, CPR0_CFGADDR, cpr, &dcr_read_cpr, &dcr_write_cpr);
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ppc_dcr_register(env, CPR0_CFGDATA, cpr, &dcr_read_cpr, &dcr_write_cpr);
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qemu_register_reset(ppc4xx_cpr_reset, cpr);
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}
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/*****************************************************************************/
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/* System DCRs */
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typedef struct ppc4xx_sdr_t ppc4xx_sdr_t;
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struct ppc4xx_sdr_t {
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uint32_t addr;
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};
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enum {
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SDR0_CFGADDR = 0x00e,
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SDR0_CFGDATA,
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SDR0_STRP0 = 0x020,
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SDR0_STRP1,
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SDR0_102 = 0x66,
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SDR0_103,
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SDR0_128 = 0x80,
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SDR0_ECID3 = 0x083,
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SDR0_DDR0 = 0x0e1,
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SDR0_USB0 = 0x320,
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};
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enum {
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PESDR0_LOOP = 0x303,
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PESDR0_RCSSET,
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PESDR0_RCSSTS,
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PESDR0_RSTSTA = 0x310,
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PESDR1_LOOP = 0x343,
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PESDR1_RCSSET,
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PESDR1_RCSSTS,
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PESDR1_RSTSTA = 0x365,
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};
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#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n)) & 0x03) << 29)
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#define SDR0_DDR0_DDRM_DDR1 0x20000000
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#define SDR0_DDR0_DDRM_DDR2 0x40000000
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static uint32_t dcr_read_sdr(void *opaque, int dcrn)
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{
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ppc4xx_sdr_t *sdr = opaque;
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uint32_t ret = 0;
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switch (dcrn) {
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case SDR0_CFGADDR:
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ret = sdr->addr;
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break;
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case SDR0_CFGDATA:
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switch (sdr->addr) {
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case SDR0_STRP0:
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ret = (0xb5 << 8) | (1 << 4) | 9;
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break;
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case SDR0_STRP1:
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ret = (5 << 29) | (2 << 26) | (1 << 24);
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break;
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case SDR0_ECID3:
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ret = 1 << 20; /* No Security/Kasumi support */
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break;
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case SDR0_DDR0:
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ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1;
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break;
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case PESDR0_RCSSET:
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case PESDR1_RCSSET:
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ret = (1 << 24) | (1 << 16);
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break;
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case PESDR0_RCSSTS:
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case PESDR1_RCSSTS:
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ret = (1 << 16) | (1 << 12);
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break;
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case PESDR0_RSTSTA:
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case PESDR1_RSTSTA:
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ret = 1;
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break;
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case PESDR0_LOOP:
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case PESDR1_LOOP:
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ret = 1 << 12;
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break;
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default:
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break;
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}
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break;
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default:
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break;
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}
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return ret;
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}
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|
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static void dcr_write_sdr(void *opaque, int dcrn, uint32_t val)
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{
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ppc4xx_sdr_t *sdr = opaque;
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switch (dcrn) {
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case SDR0_CFGADDR:
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sdr->addr = val;
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break;
|
|
case SDR0_CFGDATA:
|
|
switch (sdr->addr) {
|
|
case 0x00: /* B0CR */
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void sdr_reset(void *opaque)
|
|
{
|
|
ppc4xx_sdr_t *sdr = opaque;
|
|
|
|
sdr->addr = 0;
|
|
}
|
|
|
|
void ppc4xx_sdr_init(CPUPPCState *env)
|
|
{
|
|
ppc4xx_sdr_t *sdr;
|
|
|
|
sdr = g_malloc0(sizeof(*sdr));
|
|
qemu_register_reset(&sdr_reset, sdr);
|
|
ppc_dcr_register(env, SDR0_CFGADDR,
|
|
sdr, &dcr_read_sdr, &dcr_write_sdr);
|
|
ppc_dcr_register(env, SDR0_CFGDATA,
|
|
sdr, &dcr_read_sdr, &dcr_write_sdr);
|
|
ppc_dcr_register(env, SDR0_102,
|
|
sdr, &dcr_read_sdr, &dcr_write_sdr);
|
|
ppc_dcr_register(env, SDR0_103,
|
|
sdr, &dcr_read_sdr, &dcr_write_sdr);
|
|
ppc_dcr_register(env, SDR0_128,
|
|
sdr, &dcr_read_sdr, &dcr_write_sdr);
|
|
ppc_dcr_register(env, SDR0_USB0,
|
|
sdr, &dcr_read_sdr, &dcr_write_sdr);
|
|
}
|
|
|
|
/*****************************************************************************/
|
|
/* SDRAM controller */
|
|
typedef struct ppc4xx_sdram_t {
|
|
uint32_t addr;
|
|
int nbanks;
|
|
MemoryRegion containers[4]; /* used for clipping */
|
|
MemoryRegion *ram_memories;
|
|
hwaddr ram_bases[4];
|
|
hwaddr ram_sizes[4];
|
|
uint32_t bcr[4];
|
|
} ppc4xx_sdram_t;
|
|
|
|
enum {
|
|
SDRAM0_CFGADDR = 0x10,
|
|
SDRAM0_CFGDATA,
|
|
SDRAM_R0BAS = 0x40,
|
|
SDRAM_R1BAS,
|
|
SDRAM_R2BAS,
|
|
SDRAM_R3BAS,
|
|
SDRAM_CONF1HB = 0x45,
|
|
SDRAM_PLBADDULL = 0x4a,
|
|
SDRAM_CONF1LL = 0x4b,
|
|
SDRAM_CONFPATHB = 0x4f,
|
|
SDRAM_PLBADDUHB = 0x50,
|
|
};
|
|
|
|
/* XXX: TOFIX: some patches have made this code become inconsistent:
|
|
* there are type inconsistencies, mixing hwaddr, target_ulong
|
|
* and uint32_t
|
|
*/
|
|
static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size)
|
|
{
|
|
uint32_t bcr;
|
|
|
|
switch (ram_size) {
|
|
case (8 * MiB):
|
|
bcr = 0xffc0;
|
|
break;
|
|
case (16 * MiB):
|
|
bcr = 0xff80;
|
|
break;
|
|
case (32 * MiB):
|
|
bcr = 0xff00;
|
|
break;
|
|
case (64 * MiB):
|
|
bcr = 0xfe00;
|
|
break;
|
|
case (128 * MiB):
|
|
bcr = 0xfc00;
|
|
break;
|
|
case (256 * MiB):
|
|
bcr = 0xf800;
|
|
break;
|
|
case (512 * MiB):
|
|
bcr = 0xf000;
|
|
break;
|
|
case (1 * GiB):
|
|
bcr = 0xe000;
|
|
break;
|
|
default:
|
|
error_report("invalid RAM size " TARGET_FMT_plx, ram_size);
|
|
return 0;
|
|
}
|
|
bcr |= ram_base & 0xFF800000;
|
|
bcr |= 1;
|
|
|
|
return bcr;
|
|
}
|
|
|
|
static inline hwaddr sdram_base(uint32_t bcr)
|
|
{
|
|
return bcr & 0xFF800000;
|
|
}
|
|
|
|
static target_ulong sdram_size(uint32_t bcr)
|
|
{
|
|
target_ulong size;
|
|
int sh;
|
|
|
|
sh = 1024 - ((bcr >> 6) & 0x3ff);
|
|
size = 8 * MiB * sh;
|
|
|
|
return size;
|
|
}
|
|
|
|
static void sdram_set_bcr(ppc4xx_sdram_t *sdram,
|
|
uint32_t *bcrp, uint32_t bcr, int enabled)
|
|
{
|
|
unsigned n = bcrp - sdram->bcr;
|
|
|
|
if (*bcrp & 1) {
|
|
/* Unmap RAM */
|
|
memory_region_del_subregion(get_system_memory(),
|
|
&sdram->containers[n]);
|
|
memory_region_del_subregion(&sdram->containers[n],
|
|
&sdram->ram_memories[n]);
|
|
object_unparent(OBJECT(&sdram->containers[n]));
|
|
}
|
|
*bcrp = bcr & 0xFFDEE001;
|
|
if (enabled && (bcr & 1)) {
|
|
memory_region_init(&sdram->containers[n], NULL, "sdram-containers",
|
|
sdram_size(bcr));
|
|
memory_region_add_subregion(&sdram->containers[n], 0,
|
|
&sdram->ram_memories[n]);
|
|
memory_region_add_subregion(get_system_memory(),
|
|
sdram_base(bcr),
|
|
&sdram->containers[n]);
|
|
}
|
|
}
|
|
|
|
static void sdram_map_bcr(ppc4xx_sdram_t *sdram)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < sdram->nbanks; i++) {
|
|
if (sdram->ram_sizes[i] != 0) {
|
|
sdram_set_bcr(sdram,
|
|
&sdram->bcr[i],
|
|
sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]),
|
|
1);
|
|
} else {
|
|
sdram_set_bcr(sdram, &sdram->bcr[i], 0, 0);
|
|
}
|
|
}
|
|
}
|
|
|
|
static uint32_t dcr_read_sdram(void *opaque, int dcrn)
|
|
{
|
|
ppc4xx_sdram_t *sdram = opaque;
|
|
uint32_t ret = 0;
|
|
|
|
switch (dcrn) {
|
|
case SDRAM_R0BAS:
|
|
case SDRAM_R1BAS:
|
|
case SDRAM_R2BAS:
|
|
case SDRAM_R3BAS:
|
|
ret = sdram_bcr(sdram->ram_bases[dcrn - SDRAM_R0BAS],
|
|
sdram->ram_sizes[dcrn - SDRAM_R0BAS]);
|
|
break;
|
|
case SDRAM_CONF1HB:
|
|
case SDRAM_CONF1LL:
|
|
case SDRAM_CONFPATHB:
|
|
case SDRAM_PLBADDULL:
|
|
case SDRAM_PLBADDUHB:
|
|
break;
|
|
case SDRAM0_CFGADDR:
|
|
ret = sdram->addr;
|
|
break;
|
|
case SDRAM0_CFGDATA:
|
|
switch (sdram->addr) {
|
|
case 0x14: /* SDRAM_MCSTAT (405EX) */
|
|
case 0x1F:
|
|
ret = 0x80000000;
|
|
break;
|
|
case 0x21: /* SDRAM_MCOPT2 */
|
|
ret = 0x08000000;
|
|
break;
|
|
case 0x40: /* SDRAM_MB0CF */
|
|
ret = 0x00008001;
|
|
break;
|
|
case 0x7A: /* SDRAM_DLCR */
|
|
ret = 0x02000000;
|
|
break;
|
|
case 0xE1: /* SDR0_DDR0 */
|
|
ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
|
|
{
|
|
ppc4xx_sdram_t *sdram = opaque;
|
|
|
|
switch (dcrn) {
|
|
case SDRAM_R0BAS:
|
|
case SDRAM_R1BAS:
|
|
case SDRAM_R2BAS:
|
|
case SDRAM_R3BAS:
|
|
case SDRAM_CONF1HB:
|
|
case SDRAM_CONF1LL:
|
|
case SDRAM_CONFPATHB:
|
|
case SDRAM_PLBADDULL:
|
|
case SDRAM_PLBADDUHB:
|
|
break;
|
|
case SDRAM0_CFGADDR:
|
|
sdram->addr = val;
|
|
break;
|
|
case SDRAM0_CFGDATA:
|
|
switch (sdram->addr) {
|
|
case 0x00: /* B0CR */
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void sdram_reset(void *opaque)
|
|
{
|
|
ppc4xx_sdram_t *sdram = opaque;
|
|
|
|
sdram->addr = 0;
|
|
}
|
|
|
|
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
|
|
MemoryRegion *ram_memories,
|
|
hwaddr *ram_bases, hwaddr *ram_sizes,
|
|
int do_init)
|
|
{
|
|
ppc4xx_sdram_t *sdram;
|
|
|
|
sdram = g_malloc0(sizeof(*sdram));
|
|
sdram->nbanks = nbanks;
|
|
sdram->ram_memories = ram_memories;
|
|
memcpy(sdram->ram_bases, ram_bases, nbanks * sizeof(hwaddr));
|
|
memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(hwaddr));
|
|
qemu_register_reset(&sdram_reset, sdram);
|
|
ppc_dcr_register(env, SDRAM0_CFGADDR,
|
|
sdram, &dcr_read_sdram, &dcr_write_sdram);
|
|
ppc_dcr_register(env, SDRAM0_CFGDATA,
|
|
sdram, &dcr_read_sdram, &dcr_write_sdram);
|
|
if (do_init) {
|
|
sdram_map_bcr(sdram);
|
|
}
|
|
|
|
ppc_dcr_register(env, SDRAM_R0BAS,
|
|
sdram, &dcr_read_sdram, &dcr_write_sdram);
|
|
ppc_dcr_register(env, SDRAM_R1BAS,
|
|
sdram, &dcr_read_sdram, &dcr_write_sdram);
|
|
ppc_dcr_register(env, SDRAM_R2BAS,
|
|
sdram, &dcr_read_sdram, &dcr_write_sdram);
|
|
ppc_dcr_register(env, SDRAM_R3BAS,
|
|
sdram, &dcr_read_sdram, &dcr_write_sdram);
|
|
ppc_dcr_register(env, SDRAM_CONF1HB,
|
|
sdram, &dcr_read_sdram, &dcr_write_sdram);
|
|
ppc_dcr_register(env, SDRAM_PLBADDULL,
|
|
sdram, &dcr_read_sdram, &dcr_write_sdram);
|
|
ppc_dcr_register(env, SDRAM_CONF1LL,
|
|
sdram, &dcr_read_sdram, &dcr_write_sdram);
|
|
ppc_dcr_register(env, SDRAM_CONFPATHB,
|
|
sdram, &dcr_read_sdram, &dcr_write_sdram);
|
|
ppc_dcr_register(env, SDRAM_PLBADDUHB,
|
|
sdram, &dcr_read_sdram, &dcr_write_sdram);
|
|
}
|
|
|
|
/*****************************************************************************/
|
|
/* PLB to AHB bridge */
|
|
enum {
|
|
AHB_TOP = 0xA4,
|
|
AHB_BOT = 0xA5,
|
|
};
|
|
|
|
typedef struct ppc4xx_ahb_t {
|
|
uint32_t top;
|
|
uint32_t bot;
|
|
} ppc4xx_ahb_t;
|
|
|
|
static uint32_t dcr_read_ahb(void *opaque, int dcrn)
|
|
{
|
|
ppc4xx_ahb_t *ahb = opaque;
|
|
uint32_t ret = 0;
|
|
|
|
switch (dcrn) {
|
|
case AHB_TOP:
|
|
ret = ahb->top;
|
|
break;
|
|
case AHB_BOT:
|
|
ret = ahb->bot;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void dcr_write_ahb(void *opaque, int dcrn, uint32_t val)
|
|
{
|
|
ppc4xx_ahb_t *ahb = opaque;
|
|
|
|
switch (dcrn) {
|
|
case AHB_TOP:
|
|
ahb->top = val;
|
|
break;
|
|
case AHB_BOT:
|
|
ahb->bot = val;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void ppc4xx_ahb_reset(void *opaque)
|
|
{
|
|
ppc4xx_ahb_t *ahb = opaque;
|
|
|
|
/* No error */
|
|
ahb->top = 0;
|
|
ahb->bot = 0;
|
|
}
|
|
|
|
void ppc4xx_ahb_init(CPUPPCState *env)
|
|
{
|
|
ppc4xx_ahb_t *ahb;
|
|
|
|
ahb = g_malloc0(sizeof(*ahb));
|
|
ppc_dcr_register(env, AHB_TOP, ahb, &dcr_read_ahb, &dcr_write_ahb);
|
|
ppc_dcr_register(env, AHB_BOT, ahb, &dcr_read_ahb, &dcr_write_ahb);
|
|
qemu_register_reset(ppc4xx_ahb_reset, ahb);
|
|
}
|
|
|
|
/*****************************************************************************/
|
|
/* DMA controller */
|
|
|
|
#define DMA0_CR_CE (1 << 31)
|
|
#define DMA0_CR_PW (1 << 26 | 1 << 25)
|
|
#define DMA0_CR_DAI (1 << 24)
|
|
#define DMA0_CR_SAI (1 << 23)
|
|
#define DMA0_CR_DEC (1 << 2)
|
|
|
|
enum {
|
|
DMA0_CR = 0x00,
|
|
DMA0_CT,
|
|
DMA0_SAH,
|
|
DMA0_SAL,
|
|
DMA0_DAH,
|
|
DMA0_DAL,
|
|
DMA0_SGH,
|
|
DMA0_SGL,
|
|
|
|
DMA0_SR = 0x20,
|
|
DMA0_SGC = 0x23,
|
|
DMA0_SLP = 0x25,
|
|
DMA0_POL = 0x26,
|
|
};
|
|
|
|
typedef struct {
|
|
uint32_t cr;
|
|
uint32_t ct;
|
|
uint64_t sa;
|
|
uint64_t da;
|
|
uint64_t sg;
|
|
} PPC4xxDmaChnl;
|
|
|
|
typedef struct {
|
|
int base;
|
|
PPC4xxDmaChnl ch[4];
|
|
uint32_t sr;
|
|
} PPC4xxDmaState;
|
|
|
|
static uint32_t dcr_read_dma(void *opaque, int dcrn)
|
|
{
|
|
PPC4xxDmaState *dma = opaque;
|
|
uint32_t val = 0;
|
|
int addr = dcrn - dma->base;
|
|
int chnl = addr / 8;
|
|
|
|
switch (addr) {
|
|
case 0x00 ... 0x1f:
|
|
switch (addr % 8) {
|
|
case DMA0_CR:
|
|
val = dma->ch[chnl].cr;
|
|
break;
|
|
case DMA0_CT:
|
|
val = dma->ch[chnl].ct;
|
|
break;
|
|
case DMA0_SAH:
|
|
val = dma->ch[chnl].sa >> 32;
|
|
break;
|
|
case DMA0_SAL:
|
|
val = dma->ch[chnl].sa;
|
|
break;
|
|
case DMA0_DAH:
|
|
val = dma->ch[chnl].da >> 32;
|
|
break;
|
|
case DMA0_DAL:
|
|
val = dma->ch[chnl].da;
|
|
break;
|
|
case DMA0_SGH:
|
|
val = dma->ch[chnl].sg >> 32;
|
|
break;
|
|
case DMA0_SGL:
|
|
val = dma->ch[chnl].sg;
|
|
break;
|
|
}
|
|
break;
|
|
case DMA0_SR:
|
|
val = dma->sr;
|
|
break;
|
|
default:
|
|
qemu_log_mask(LOG_UNIMP, "%s: unimplemented register %x (%d, %x)\n",
|
|
__func__, dcrn, chnl, addr);
|
|
}
|
|
|
|
return val;
|
|
}
|
|
|
|
static void dcr_write_dma(void *opaque, int dcrn, uint32_t val)
|
|
{
|
|
PPC4xxDmaState *dma = opaque;
|
|
int addr = dcrn - dma->base;
|
|
int chnl = addr / 8;
|
|
|
|
switch (addr) {
|
|
case 0x00 ... 0x1f:
|
|
switch (addr % 8) {
|
|
case DMA0_CR:
|
|
dma->ch[chnl].cr = val;
|
|
if (val & DMA0_CR_CE) {
|
|
int count = dma->ch[chnl].ct & 0xffff;
|
|
|
|
if (count) {
|
|
int width, i, sidx, didx;
|
|
uint8_t *rptr, *wptr;
|
|
hwaddr rlen, wlen;
|
|
|
|
sidx = didx = 0;
|
|
width = 1 << ((val & DMA0_CR_PW) >> 25);
|
|
rptr = cpu_physical_memory_map(dma->ch[chnl].sa, &rlen, 0);
|
|
wptr = cpu_physical_memory_map(dma->ch[chnl].da, &wlen, 1);
|
|
if (rptr && wptr) {
|
|
if (!(val & DMA0_CR_DEC) &&
|
|
val & DMA0_CR_SAI && val & DMA0_CR_DAI) {
|
|
/* optimise common case */
|
|
memmove(wptr, rptr, count * width);
|
|
sidx = didx = count * width;
|
|
} else {
|
|
/* do it the slow way */
|
|
for (sidx = didx = i = 0; i < count; i++) {
|
|
uint64_t v = ldn_le_p(rptr + sidx, width);
|
|
stn_le_p(wptr + didx, width, v);
|
|
if (val & DMA0_CR_SAI) {
|
|
sidx += width;
|
|
}
|
|
if (val & DMA0_CR_DAI) {
|
|
didx += width;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
if (wptr) {
|
|
cpu_physical_memory_unmap(wptr, wlen, 1, didx);
|
|
}
|
|
if (rptr) {
|
|
cpu_physical_memory_unmap(rptr, rlen, 0, sidx);
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
case DMA0_CT:
|
|
dma->ch[chnl].ct = val;
|
|
break;
|
|
case DMA0_SAH:
|
|
dma->ch[chnl].sa &= 0xffffffffULL;
|
|
dma->ch[chnl].sa |= (uint64_t)val << 32;
|
|
break;
|
|
case DMA0_SAL:
|
|
dma->ch[chnl].sa &= 0xffffffff00000000ULL;
|
|
dma->ch[chnl].sa |= val;
|
|
break;
|
|
case DMA0_DAH:
|
|
dma->ch[chnl].da &= 0xffffffffULL;
|
|
dma->ch[chnl].da |= (uint64_t)val << 32;
|
|
break;
|
|
case DMA0_DAL:
|
|
dma->ch[chnl].da &= 0xffffffff00000000ULL;
|
|
dma->ch[chnl].da |= val;
|
|
break;
|
|
case DMA0_SGH:
|
|
dma->ch[chnl].sg &= 0xffffffffULL;
|
|
dma->ch[chnl].sg |= (uint64_t)val << 32;
|
|
break;
|
|
case DMA0_SGL:
|
|
dma->ch[chnl].sg &= 0xffffffff00000000ULL;
|
|
dma->ch[chnl].sg |= val;
|
|
break;
|
|
}
|
|
break;
|
|
case DMA0_SR:
|
|
dma->sr &= ~val;
|
|
break;
|
|
default:
|
|
qemu_log_mask(LOG_UNIMP, "%s: unimplemented register %x (%d, %x)\n",
|
|
__func__, dcrn, chnl, addr);
|
|
}
|
|
}
|
|
|
|
static void ppc4xx_dma_reset(void *opaque)
|
|
{
|
|
PPC4xxDmaState *dma = opaque;
|
|
int dma_base = dma->base;
|
|
|
|
memset(dma, 0, sizeof(*dma));
|
|
dma->base = dma_base;
|
|
}
|
|
|
|
void ppc4xx_dma_init(CPUPPCState *env, int dcr_base)
|
|
{
|
|
PPC4xxDmaState *dma;
|
|
int i;
|
|
|
|
dma = g_malloc0(sizeof(*dma));
|
|
dma->base = dcr_base;
|
|
qemu_register_reset(&ppc4xx_dma_reset, dma);
|
|
for (i = 0; i < 4; i++) {
|
|
ppc_dcr_register(env, dcr_base + i * 8 + DMA0_CR,
|
|
dma, &dcr_read_dma, &dcr_write_dma);
|
|
ppc_dcr_register(env, dcr_base + i * 8 + DMA0_CT,
|
|
dma, &dcr_read_dma, &dcr_write_dma);
|
|
ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SAH,
|
|
dma, &dcr_read_dma, &dcr_write_dma);
|
|
ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SAL,
|
|
dma, &dcr_read_dma, &dcr_write_dma);
|
|
ppc_dcr_register(env, dcr_base + i * 8 + DMA0_DAH,
|
|
dma, &dcr_read_dma, &dcr_write_dma);
|
|
ppc_dcr_register(env, dcr_base + i * 8 + DMA0_DAL,
|
|
dma, &dcr_read_dma, &dcr_write_dma);
|
|
ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SGH,
|
|
dma, &dcr_read_dma, &dcr_write_dma);
|
|
ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SGL,
|
|
dma, &dcr_read_dma, &dcr_write_dma);
|
|
}
|
|
ppc_dcr_register(env, dcr_base + DMA0_SR,
|
|
dma, &dcr_read_dma, &dcr_write_dma);
|
|
ppc_dcr_register(env, dcr_base + DMA0_SGC,
|
|
dma, &dcr_read_dma, &dcr_write_dma);
|
|
ppc_dcr_register(env, dcr_base + DMA0_SLP,
|
|
dma, &dcr_read_dma, &dcr_write_dma);
|
|
ppc_dcr_register(env, dcr_base + DMA0_POL,
|
|
dma, &dcr_read_dma, &dcr_write_dma);
|
|
}
|
|
|
|
/*****************************************************************************/
|
|
/* PCI Express controller */
|
|
/* FIXME: This is not complete and does not work, only implemented partially
|
|
* to allow firmware and guests to find an empty bus. Cards should use PCI.
|
|
*/
|
|
#include "hw/pci/pcie_host.h"
|
|
|
|
#define TYPE_PPC460EX_PCIE_HOST "ppc460ex-pcie-host"
|
|
#define PPC460EX_PCIE_HOST(obj) \
|
|
OBJECT_CHECK(PPC460EXPCIEState, (obj), TYPE_PPC460EX_PCIE_HOST)
|
|
|
|
typedef struct PPC460EXPCIEState {
|
|
PCIExpressHost host;
|
|
|
|
MemoryRegion iomem;
|
|
qemu_irq irq[4];
|
|
int32_t dcrn_base;
|
|
|
|
uint64_t cfg_base;
|
|
uint32_t cfg_mask;
|
|
uint64_t msg_base;
|
|
uint32_t msg_mask;
|
|
uint64_t omr1_base;
|
|
uint64_t omr1_mask;
|
|
uint64_t omr2_base;
|
|
uint64_t omr2_mask;
|
|
uint64_t omr3_base;
|
|
uint64_t omr3_mask;
|
|
uint64_t reg_base;
|
|
uint32_t reg_mask;
|
|
uint32_t special;
|
|
uint32_t cfg;
|
|
} PPC460EXPCIEState;
|
|
|
|
#define DCRN_PCIE0_BASE 0x100
|
|
#define DCRN_PCIE1_BASE 0x120
|
|
|
|
enum {
|
|
PEGPL_CFGBAH = 0x0,
|
|
PEGPL_CFGBAL,
|
|
PEGPL_CFGMSK,
|
|
PEGPL_MSGBAH,
|
|
PEGPL_MSGBAL,
|
|
PEGPL_MSGMSK,
|
|
PEGPL_OMR1BAH,
|
|
PEGPL_OMR1BAL,
|
|
PEGPL_OMR1MSKH,
|
|
PEGPL_OMR1MSKL,
|
|
PEGPL_OMR2BAH,
|
|
PEGPL_OMR2BAL,
|
|
PEGPL_OMR2MSKH,
|
|
PEGPL_OMR2MSKL,
|
|
PEGPL_OMR3BAH,
|
|
PEGPL_OMR3BAL,
|
|
PEGPL_OMR3MSKH,
|
|
PEGPL_OMR3MSKL,
|
|
PEGPL_REGBAH,
|
|
PEGPL_REGBAL,
|
|
PEGPL_REGMSK,
|
|
PEGPL_SPECIAL,
|
|
PEGPL_CFG,
|
|
};
|
|
|
|
static uint32_t dcr_read_pcie(void *opaque, int dcrn)
|
|
{
|
|
PPC460EXPCIEState *state = opaque;
|
|
uint32_t ret = 0;
|
|
|
|
switch (dcrn - state->dcrn_base) {
|
|
case PEGPL_CFGBAH:
|
|
ret = state->cfg_base >> 32;
|
|
break;
|
|
case PEGPL_CFGBAL:
|
|
ret = state->cfg_base;
|
|
break;
|
|
case PEGPL_CFGMSK:
|
|
ret = state->cfg_mask;
|
|
break;
|
|
case PEGPL_MSGBAH:
|
|
ret = state->msg_base >> 32;
|
|
break;
|
|
case PEGPL_MSGBAL:
|
|
ret = state->msg_base;
|
|
break;
|
|
case PEGPL_MSGMSK:
|
|
ret = state->msg_mask;
|
|
break;
|
|
case PEGPL_OMR1BAH:
|
|
ret = state->omr1_base >> 32;
|
|
break;
|
|
case PEGPL_OMR1BAL:
|
|
ret = state->omr1_base;
|
|
break;
|
|
case PEGPL_OMR1MSKH:
|
|
ret = state->omr1_mask >> 32;
|
|
break;
|
|
case PEGPL_OMR1MSKL:
|
|
ret = state->omr1_mask;
|
|
break;
|
|
case PEGPL_OMR2BAH:
|
|
ret = state->omr2_base >> 32;
|
|
break;
|
|
case PEGPL_OMR2BAL:
|
|
ret = state->omr2_base;
|
|
break;
|
|
case PEGPL_OMR2MSKH:
|
|
ret = state->omr2_mask >> 32;
|
|
break;
|
|
case PEGPL_OMR2MSKL:
|
|
ret = state->omr3_mask;
|
|
break;
|
|
case PEGPL_OMR3BAH:
|
|
ret = state->omr3_base >> 32;
|
|
break;
|
|
case PEGPL_OMR3BAL:
|
|
ret = state->omr3_base;
|
|
break;
|
|
case PEGPL_OMR3MSKH:
|
|
ret = state->omr3_mask >> 32;
|
|
break;
|
|
case PEGPL_OMR3MSKL:
|
|
ret = state->omr3_mask;
|
|
break;
|
|
case PEGPL_REGBAH:
|
|
ret = state->reg_base >> 32;
|
|
break;
|
|
case PEGPL_REGBAL:
|
|
ret = state->reg_base;
|
|
break;
|
|
case PEGPL_REGMSK:
|
|
ret = state->reg_mask;
|
|
break;
|
|
case PEGPL_SPECIAL:
|
|
ret = state->special;
|
|
break;
|
|
case PEGPL_CFG:
|
|
ret = state->cfg;
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void dcr_write_pcie(void *opaque, int dcrn, uint32_t val)
|
|
{
|
|
PPC460EXPCIEState *s = opaque;
|
|
uint64_t size;
|
|
|
|
switch (dcrn - s->dcrn_base) {
|
|
case PEGPL_CFGBAH:
|
|
s->cfg_base = ((uint64_t)val << 32) | (s->cfg_base & 0xffffffff);
|
|
break;
|
|
case PEGPL_CFGBAL:
|
|
s->cfg_base = (s->cfg_base & 0xffffffff00000000ULL) | val;
|
|
break;
|
|
case PEGPL_CFGMSK:
|
|
s->cfg_mask = val;
|
|
size = ~(val & 0xfffffffe) + 1;
|
|
qemu_mutex_lock_iothread();
|
|
pcie_host_mmcfg_update(PCIE_HOST_BRIDGE(s), val & 1, s->cfg_base, size);
|
|
qemu_mutex_unlock_iothread();
|
|
break;
|
|
case PEGPL_MSGBAH:
|
|
s->msg_base = ((uint64_t)val << 32) | (s->msg_base & 0xffffffff);
|
|
break;
|
|
case PEGPL_MSGBAL:
|
|
s->msg_base = (s->msg_base & 0xffffffff00000000ULL) | val;
|
|
break;
|
|
case PEGPL_MSGMSK:
|
|
s->msg_mask = val;
|
|
break;
|
|
case PEGPL_OMR1BAH:
|
|
s->omr1_base = ((uint64_t)val << 32) | (s->omr1_base & 0xffffffff);
|
|
break;
|
|
case PEGPL_OMR1BAL:
|
|
s->omr1_base = (s->omr1_base & 0xffffffff00000000ULL) | val;
|
|
break;
|
|
case PEGPL_OMR1MSKH:
|
|
s->omr1_mask = ((uint64_t)val << 32) | (s->omr1_mask & 0xffffffff);
|
|
break;
|
|
case PEGPL_OMR1MSKL:
|
|
s->omr1_mask = (s->omr1_mask & 0xffffffff00000000ULL) | val;
|
|
break;
|
|
case PEGPL_OMR2BAH:
|
|
s->omr2_base = ((uint64_t)val << 32) | (s->omr2_base & 0xffffffff);
|
|
break;
|
|
case PEGPL_OMR2BAL:
|
|
s->omr2_base = (s->omr2_base & 0xffffffff00000000ULL) | val;
|
|
break;
|
|
case PEGPL_OMR2MSKH:
|
|
s->omr2_mask = ((uint64_t)val << 32) | (s->omr2_mask & 0xffffffff);
|
|
break;
|
|
case PEGPL_OMR2MSKL:
|
|
s->omr2_mask = (s->omr2_mask & 0xffffffff00000000ULL) | val;
|
|
break;
|
|
case PEGPL_OMR3BAH:
|
|
s->omr3_base = ((uint64_t)val << 32) | (s->omr3_base & 0xffffffff);
|
|
break;
|
|
case PEGPL_OMR3BAL:
|
|
s->omr3_base = (s->omr3_base & 0xffffffff00000000ULL) | val;
|
|
break;
|
|
case PEGPL_OMR3MSKH:
|
|
s->omr3_mask = ((uint64_t)val << 32) | (s->omr3_mask & 0xffffffff);
|
|
break;
|
|
case PEGPL_OMR3MSKL:
|
|
s->omr3_mask = (s->omr3_mask & 0xffffffff00000000ULL) | val;
|
|
break;
|
|
case PEGPL_REGBAH:
|
|
s->reg_base = ((uint64_t)val << 32) | (s->reg_base & 0xffffffff);
|
|
break;
|
|
case PEGPL_REGBAL:
|
|
s->reg_base = (s->reg_base & 0xffffffff00000000ULL) | val;
|
|
break;
|
|
case PEGPL_REGMSK:
|
|
s->reg_mask = val;
|
|
/* FIXME: how is size encoded? */
|
|
size = (val == 0x7001 ? 4096 : ~(val & 0xfffffffe) + 1);
|
|
break;
|
|
case PEGPL_SPECIAL:
|
|
s->special = val;
|
|
break;
|
|
case PEGPL_CFG:
|
|
s->cfg = val;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void ppc460ex_set_irq(void *opaque, int irq_num, int level)
|
|
{
|
|
PPC460EXPCIEState *s = opaque;
|
|
qemu_set_irq(s->irq[irq_num], level);
|
|
}
|
|
|
|
static void ppc460ex_pcie_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
PPC460EXPCIEState *s = PPC460EX_PCIE_HOST(dev);
|
|
PCIHostState *pci = PCI_HOST_BRIDGE(dev);
|
|
int i, id;
|
|
char buf[16];
|
|
|
|
switch (s->dcrn_base) {
|
|
case DCRN_PCIE0_BASE:
|
|
id = 0;
|
|
break;
|
|
case DCRN_PCIE1_BASE:
|
|
id = 1;
|
|
break;
|
|
default:
|
|
error_setg(errp, "invalid PCIe DCRN base");
|
|
return;
|
|
}
|
|
snprintf(buf, sizeof(buf), "pcie%d-io", id);
|
|
memory_region_init(&s->iomem, OBJECT(s), buf, UINT64_MAX);
|
|
for (i = 0; i < 4; i++) {
|
|
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
|
|
}
|
|
snprintf(buf, sizeof(buf), "pcie.%d", id);
|
|
pci->bus = pci_register_root_bus(DEVICE(s), buf, ppc460ex_set_irq,
|
|
pci_swizzle_map_irq_fn, s, &s->iomem,
|
|
get_system_io(), 0, 4, TYPE_PCIE_BUS);
|
|
}
|
|
|
|
static Property ppc460ex_pcie_props[] = {
|
|
DEFINE_PROP_INT32("dcrn-base", PPC460EXPCIEState, dcrn_base, -1),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void ppc460ex_pcie_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
|
dc->realize = ppc460ex_pcie_realize;
|
|
dc->props = ppc460ex_pcie_props;
|
|
dc->hotpluggable = false;
|
|
}
|
|
|
|
static const TypeInfo ppc460ex_pcie_host_info = {
|
|
.name = TYPE_PPC460EX_PCIE_HOST,
|
|
.parent = TYPE_PCIE_HOST_BRIDGE,
|
|
.instance_size = sizeof(PPC460EXPCIEState),
|
|
.class_init = ppc460ex_pcie_class_init,
|
|
};
|
|
|
|
static void ppc460ex_pcie_register(void)
|
|
{
|
|
type_register_static(&ppc460ex_pcie_host_info);
|
|
}
|
|
|
|
type_init(ppc460ex_pcie_register)
|
|
|
|
static void ppc460ex_pcie_register_dcrs(PPC460EXPCIEState *s, CPUPPCState *env)
|
|
{
|
|
ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGBAH, s,
|
|
&dcr_read_pcie, &dcr_write_pcie);
|
|
ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGBAL, s,
|
|
&dcr_read_pcie, &dcr_write_pcie);
|
|
ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGMSK, s,
|
|
&dcr_read_pcie, &dcr_write_pcie);
|
|
ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGBAH, s,
|
|
&dcr_read_pcie, &dcr_write_pcie);
|
|
ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGBAL, s,
|
|
&dcr_read_pcie, &dcr_write_pcie);
|
|
ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGMSK, s,
|
|
&dcr_read_pcie, &dcr_write_pcie);
|
|
ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1BAH, s,
|
|
&dcr_read_pcie, &dcr_write_pcie);
|
|
ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1BAL, s,
|
|
&dcr_read_pcie, &dcr_write_pcie);
|
|
ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1MSKH, s,
|
|
&dcr_read_pcie, &dcr_write_pcie);
|
|
ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1MSKL, s,
|
|
&dcr_read_pcie, &dcr_write_pcie);
|
|
ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2BAH, s,
|
|
&dcr_read_pcie, &dcr_write_pcie);
|
|
ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2BAL, s,
|
|
&dcr_read_pcie, &dcr_write_pcie);
|
|
ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2MSKH, s,
|
|
&dcr_read_pcie, &dcr_write_pcie);
|
|
ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2MSKL, s,
|
|
&dcr_read_pcie, &dcr_write_pcie);
|
|
ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3BAH, s,
|
|
&dcr_read_pcie, &dcr_write_pcie);
|
|
ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3BAL, s,
|
|
&dcr_read_pcie, &dcr_write_pcie);
|
|
ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3MSKH, s,
|
|
&dcr_read_pcie, &dcr_write_pcie);
|
|
ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3MSKL, s,
|
|
&dcr_read_pcie, &dcr_write_pcie);
|
|
ppc_dcr_register(env, s->dcrn_base + PEGPL_REGBAH, s,
|
|
&dcr_read_pcie, &dcr_write_pcie);
|
|
ppc_dcr_register(env, s->dcrn_base + PEGPL_REGBAL, s,
|
|
&dcr_read_pcie, &dcr_write_pcie);
|
|
ppc_dcr_register(env, s->dcrn_base + PEGPL_REGMSK, s,
|
|
&dcr_read_pcie, &dcr_write_pcie);
|
|
ppc_dcr_register(env, s->dcrn_base + PEGPL_SPECIAL, s,
|
|
&dcr_read_pcie, &dcr_write_pcie);
|
|
ppc_dcr_register(env, s->dcrn_base + PEGPL_CFG, s,
|
|
&dcr_read_pcie, &dcr_write_pcie);
|
|
}
|
|
|
|
void ppc460ex_pcie_init(CPUPPCState *env)
|
|
{
|
|
DeviceState *dev;
|
|
|
|
dev = qdev_create(NULL, TYPE_PPC460EX_PCIE_HOST);
|
|
qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE0_BASE);
|
|
qdev_init_nofail(dev);
|
|
object_property_set_bool(OBJECT(dev), true, "realized", NULL);
|
|
ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env);
|
|
|
|
dev = qdev_create(NULL, TYPE_PPC460EX_PCIE_HOST);
|
|
qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE1_BASE);
|
|
qdev_init_nofail(dev);
|
|
object_property_set_bool(OBJECT(dev), true, "realized", NULL);
|
|
ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env);
|
|
}
|